Intel Corporation

Travis M Eiles

Qing Ma

Krishna Seshan

Jin Hyung Lee

Harry H Fujimoto

Changhong Dai

Shiuh-Wuu Lee

Mario J Paniccia

David N Shykind

Stefan Rusu

Timothy J Maloney

Jeremy A Rowlette

Gary Leonard Woods

Patrick Pardy

Dean J Grannes

Amir Raveh

Rajiv Giridharagopal

Steven G Seidel

Evgeny Gregory Nisenboim

Cameron Wagner

A probe assembly for analyzing a test device that includes a housing with an electron source disposed therein for emitting primary electrons. A photon source is positioned to emit photons that strike the electron source such that when the photons strike the electron source, the electron source emits the primary electrons. Detection circuitry is provided that is configured to detect secondary electrons emitted from a test device of a test assembly and to form an excitation waveform.

Probe assembly with high bandwidth beam

Visible laser probing is described. In one example a probe device has a laser configured to provide a laser beam at a visible wavelength, an objective lens positioned in front of the laser to focus the laser beam on an active region of an integrated circuit through a back side of an integrated circuit die, and a detector positioned to receive a reflected laser beam reflected from the active region through a back side of the die, through the objective lens. The detector is configured to detect an amplitude modulation of the reflected laser beam wherein the amplitude modulation is attributable to the electric field at the active region.

Visible laser probing for circuit debug and defect analysis

Embodiments allow for uniform die cooling or heating with a solid immersion lens equipped microscope over a larger temperature range than is currently attainable using liquid coolant. The SIL tip is insulated from the rest of the objective body to realize a controllable temperature. This thermal control may be done by convection or Joule heating. If the tip is to be cooled, cold gas may be injected through channels around the tip and fins. If the tip is to be heated, hot gas may be injected around the tip and finsor an electrical heater may be thermal anchored to the tip and a current passed through it to deliver power.

Thermally controlled sold immersion lens fixture

An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.

Isolation structure configurations for modifying stresses in semiconductor devices

Integrated circuit and integrated circuit device diagnostic methods and apparatus in accordance with the present invention are provided. The IC is operated to produce an output marginally above a pass-fail threshold for a particular performance criteria. The IC is made to fail that criteria by inducing an electrical stress in an IC device that is of marginal design for that particular criteria. The electrical stress acts to minutely degrade the performance of the IC device driving the IC below the pass-fail threshold. When each IC device is stressed in accordance with the embodiments of the present invention, marginal IC devices are identified to enable the design to be modified. The induced electrical stress is non-destructive to the IC device and IC, which permits a repeatable diagnostic process, as well as allows for the diagnostic testing of other IC devices in the same microcircuit.

Device speed alteration by electron-hole pair injection and device heating

An integrated circuit device having an embedded heat slug. The integrated circuit device comprises, in one embodiment, a semiconductor substrate having a frontside surface and a backside surface. The semiconductor substrate includes an integrated circuit on the frontside surface. A heat slug is disposed in an opening in the backside surface of the semiconductor substrate adjacent the integrated circuit.

Integrated circuit device having an embedded heat slug

An integrated circuit device having an embedded heat slug. The integrated circuit device comprises, in one embodiment, a semiconductor substrate having a frontside surface and backside surface. The semiconductor substrate includes an integrated circuit on the frontside surface. A heat slug is disposed in an opening in the backside surface of the semiconductor substrate adjacent the integrated circuit.

A method is provided for manufacturing a die. A supply voltage is provided to a power plane of a selected integrated circuit, formed in and on a semiconductor substrate, having a selected design, so that a respective test current flows through a plurality of test elements, of the selected integrated circuit, each being connected to a respective test point on the power plane, the test points being spaced from one another. A magnitude of each respective test current is detected. A respective test voltage is calculated at each respective test point utilizing the respective magnitude of the respective test current flowing through the respective test element connected to a respective test point. The respective test voltages are utilized to determine at which ones of the test points the respective test voltages are more than a predetermined maximum below a supply voltage. The electric design is altered to an altered electric design if any of the test voltages are below a predetermined minimum below the supply voltage. An integrated circuit having the altered design is then manufactured on another semiconductor substrate.

Semiconductor die manufacture method to limit a voltage drop on a power plane thereof by noninvasively measuring voltages on a power plane

Electrostatic discharge protection circuits adapted for use in low voltage CMOS processes have at least one PFET in the primary charge conduction path, and timer circuits configured to enable the primary conduction path during ESD events and to disable the primary conduction path during steady state conditions. In a further aspect of the present invention, bias circuits for maintaining steady state gate voltages below the dielectric breakdown level are included. In a still further aspect of the present invention a bridge circuit couples a first power supply node to a second power supply node, where the second power supply node is coupled to an ESD protection circuit.

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San Jose, CA, United States of America

Travis M Eiles