Achronix Semiconductor Corporation

Travis Johnson

Kent Orthner

Sarma Jonnavithula

Quinn Jacobson

Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

Processing of ethernet packets at a programmable integrated circuit

A mirror extension arm for a wide-load truck is an apparatus that allows a driver of the wide-load truck to have a wider peripheral vision range and eliminates blind spots. The apparatus includes an extension tube, a slide bar, a mounting spindle, at least one locking clamp, and a fastening mechanism. The extension bar and the slide bar offset a secondary side mirror from a corresponding side of the wide-load truck. The secondary side mirror is preferably positioned beside an existing side mirror. The extension bar connects with a bracket of the existing side mirror, and the slide bar varies the distance of the secondary side mirror and existing side mirror. The mounting spindle upholds the secondary side mirror. The at least one locking clamp attaches the extension bar with the bracket of the existing side mirror. The fastening mechanism locks the slide bar along the extension tube.

Mirror extension arm for a wide-load truck

A fence installation apparatus that is operably coupled to a vehicle wherein the vehicle is traversed along a desired fence line while the fence apparatus is utilized to provide installation of a fence. The fence installation apparatus includes a drive assembly support frame having a rear support member and front support member. The rear support member and the front support member having operably coupled thereto a first drive member and a second drive member. The first drive member and second drive member are configured to drive fence posts into the ground. The fence installation apparatus further includes a first wire dispenser that is rotatably mounted in order to provide distribution of a wire during fence installation. A second wire dispenser is further included to dispense a second wire and further has a pole mount and pole member coupled thereto for distribution of fence accessories.

Fence installation apparatus

Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns, clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

Methods, systems, and computer programs are presented for distributing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an iNOC comprising iNOC rows and iNOC columns; a set of clusters coupled to the iNOC, each cluster comprising a vertical network access point (NAP) for iNOC column communications, a horizontal NAP for iNOC row communications, a valid signal, and programmable logic, where the vertical NAP is connected to the horizontal NAP when the valid signal is activated; and an Ethernet controller coupled to the iNOC, the Ethernet controller configurable to send Ethernet-packet segments to the vertical NAPs.

Flexible routing of network data within a programmable integrated circuit

Methods, systems, and computer programs are presented for routing packets on a network on chip (NOC) within a programmable integrated circuit. One programmable integrated circuit comprises a plurality of clusters disposed on a plurality of cluster rows and a plurality of cluster columns, an internal network on chip (iNOC) comprising iNOC rows and iNOC columns, an external network on chip (eNOC) connected to the iNOC rows and the iNOC columns, and a field programmable gate array Control Unit (FCU) for configuring programmable logic in the plurality of clusters based on a first configuration received by the FCU. The FCU is connected to the eNOC, where the FCU communicates with the plurality of clusters via the iNOC and the eNOC. The FCU is configured for receiving a second configuration from the programmable logic in the plurality of clusters for reconfiguring a component of the programmable integrated circuit.

Reconfigurable programmable integrated circuit with on-chip network

Methods, systems, and computer programs are presented for implementing a network on chip (NOC). One programmable integrated circuit comprises a plurality of clusters, an internal network on chip (iNOC), and an external network on chip (eNOC) outside the plurality of clusters. The plurality of clusters is disposed on a plurality of cluster rows and a plurality of cluster columns, each cluster comprising programmable logic. Further, the iNOC comprises iNOC rows and iNOC columns. Each iNOC row is configured for transporting data and comprising connections to clusters in a cluster row and the eNOC, and each iNOC column is configured for transporting data and comprising connections to clusters in a cluster column and the eNOC.

Growing community of inventors

Santa Clara, CA, United States of America

Travis Johnson