International Business Machines Corporation

Travis James Pizel

Thomas R Sand

Gregory Michael Nordstrom

Justin King

John Ronald Oberly, Iii

Chetan Mehta

Daniel Ernest Hurlimann

Fernando Pizzano

Sean Thomas Brownlow

Anjan Kumar Guttahalli Krishna

Victor Anthony Garibay

Naveen Rathi

Steven Mark Thurber

Charles Scott Graham

Randal Craig Swanberg

Timothy J Schimke

John Thomas O'Quin, Ii

William Alan Thompson

Shawn Michael Lambeth

Daniel Robert Lipps

Vlctor A Garibay

Swathi M Bhattiprolu

Dynamic I/O translation table allocation for SR-IOV enabled I/O adapters including receiving an instruction to transition the SR-IOV adapter to shared mode; determining, using a configuration file for the SR-IOV adapter, memory requirements for an I/O translation table; comparing the memory requirements for the I/O translation table to memory currently allocated for use by the SR-IOV adapter; based on the comparing the memory requirements for the I/O translation table to the memory currently allocated for use by the SR-IOV adapter, determining that the memory currently allocated for use by the SR-IOV adapter is insufficient to store the I/O translation table and determining an additional amount of memory required to store the I/O translation table; and allocating, at runtime, the additional amount of memory for storing the I/O translation table.

Dynamic I/O translation table allocation for single root input output virtualization enabled I/O adapters

Techniques are disclosed herein for paging I/O translation table entries. A host bridge of system hardware receives a request to fetch a first segment of an I/O translation table associated with one of a plurality of logical partitions executing in a computing system. The host bridge identifies a control register associated with the first segment. Upon determining that the first segment is paged out to the storage volume, a second segment is paged out from a location in memory to the storage volume. The first segment is paged in to the location.

Use efficiency of platform memory resources through firmware managed I/O translation table paging

A system and method dynamically allocate address translation tables for direct memory access windows by donating logical memory blocks to allocate to the address translation tables. A dynamic address translation table allocation module dynamically changes the allocation of memory to the address translation tables without a platform or partition reboot. A portion of the dynamic address translation table allocation module may reside in the hypervisor and in the partition and communicate to dynamically allocate memory to the address translation tables. The dynamic address translation table allocation module in the partition may donate logical memory blocks to the hypervisor to increase the allocation of memory to the address translation tables.

Dynamic address translation table allocation

Techniques are disclosed herein for paging I/O translation table entries. A host bridge of system hardware receives a request to fetch a first segment of an I/O translation table associated with one of a plurality of logical partitions executing in a computing system. The host bridge identifies a control register associated with the first segment. The control register includes a time base and an indication of whether the first segment is paged out to a storage volume. Upon determining that the first segment is paged out to the storage volume, a second segment is paged out from a location in memory to the storage volume. The first segment is paged in to the location.

A dynamic DMA window mechanism can resize DMA windows dynamically by increasing one DMA window at the expense of reducing a neighboring DMA window. The dynamic DMA window mechanism can decide to dynamically resize DMA windows based on a request from a system administrator, based on a request by an operating system device driver for an I/O adapter, or based on a performance monitor determining such a resizing would benefit system performance. Once one DMA window has been increased by allocating a portion of a donor DMA window, device drivers for the I/O devices corresponding to the two windows are updated to reflect the new DMA window sizes.

Dynamically resizing direct memory access (DMA) windows

A computer-implemented method may include assigning an address translation table to a peripheral component interconnect host bridge and determining that an input/output adapter accessible to the peripheral component interconnect host bridge is configured as a virtualized adapter to provide a plurality of virtual functions to a plurality of logical partitions. In response to determining that the input/output adapter is configured as the virtualized adapter, the address translation table may be subdivided to enable the plurality of virtual functions to access the memory of at least one logical partition of the plurality of logical partitions.

Address translation table to enable access to virtualized functions

A computing device may merge two translation tables used when performing a DMA operation into a single, combined translation table. To merge the translation tables, the computing device may update a register in the IOMMU to include a pointer to the combined translation table. In addition, the IOMMU may clear one of the registers from having a pointer to one of the merged translation table. Doing so means the entries in this translation table are now no longer assigned. The IOMMU may update the register with the pointer to the combined translation table to include the unassigned entries in the combined translation table. In this manner, the entries from the two translation tables are merged into the single, combined table. The combined translation table may be owned or assigned to a service provider that originally owned one of the merged translation tables or to a completely different service provider.

Merging direct memory access windows

A computing device may split a translation table used when performing a DMA operation into two different translation tables. To split the translation table, the computing device may update the registers in the IOMMU to include pointers to the two different translation tables. For example, the IOMMU may update one register to point to the same starting address as the original translation table but assign a shorter length (i.e., fewer entries) to that table. The extra entries may then be used to form the other translation table by adding a new pointer to one of the IOMMU registers. The two translation tables may be owned by the same service provider or two different service providers. Alternatively, the computing device may assign the two tables to the same service provider which in turn assigns the tables to respective client devices executed by the service provider.

Splitting direct memory access windows

In response to detecting a PCI host bridge (PHB), a first address translation table may be allocated in a first portion of a memory. The first address translation table may be associated with the PHB. If an input/output adapter accessible to the PHB is configured as a virtualized adapter, a first table manager may be assigned to manage the first address translation table. The first address translation table may be configured for an initial number of virtual functions. If a requested number of virtual functions is greater than the initial number of virtual functions, additional virtual functions may be configured. A second address translation table may be allocated in a second portion of the memory. The second portion of the memory may be non-contiguous with reference to the first portion of the memory. Entries may be created in the second address translation table for the additional virtual functions.

Address translation table to enable access to virtual functions

A computer-implemented method may include determining that a slot coupled to a peripheral component interconnect host bridge is occupied by an input/output adapter. The computer-implemented method may include determining one or more characteristics of the input/output adapter and determining whether the input/output adapter is capable of using additional memory based on the one or more characteristics of the input/output adapter. The computer-implemented method may also include allocating the additional memory for the input/output adapter in response to determining that the input/output adapter is capable of using the additional memory.

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Rochester, MN, United States of America

Travis James Pizel