USA As Represented by Secretary of the Navy

University of California

Northrop Grumman Systems Corporation

Travis J Anderson

Francis J Kub

Karl D Hobart

Andrew D Koehler

Marko J Tadjer

Michael Anthony Mastro

Tatyana I Feygelson

Charles R Eddy, Jr

Boris N Feigelson

Virginia D Wheeler

Alan G Jacobs

Jennifer K Hite

Boris N Feygelson

James C Gallagher

Bradford B Pate

Mark Goorsky

Jordan D Greenlee

Rachael L Myers-Ward

Joshua D Caldwell

Neeraj Nepal

Samuel Graham, Jr

Sandra C Hangarter

Tingyu Bai

Yekan Wang

Mona A Ebrish

Geoffrey M Foster

Lunet E Luna

Zhe Cheng

Luke Yates

Vincent Gambin

Steven R Huard

John P Blomberg

Ioulia Smorchkova

Gregory Todd Lewis

Daniel G Georgiev

Matthew Porter

Rajinder S Sandhu

Eugene I Imhoff

Prakash Pandey

Tolen Michael Nelson

Raghav Khanna

Michael Robert Hontz

Kevin B Henke

Justin O Byers

David Shahin

Jeff McKay

Joseph L Dobmeier

A technique for selective-area diffusion doping of III-N epitaxial material layers and for fabricating power device structures utilizing this technique. Dopant species such as Mg are introduced into the III-N material layer and are diffused into the III-N material by annealing under stable or metastable conditions. The dopant species can be introduced via deposition of a metal or alloy layer containing such species using sputtering, e-beam evaporation or other technique known to those skilled in the art. The dopant material layer is capped with a thermally stable layer to prevent decomposition and out-diffusion, and then is annealed under stable or metastable conditions to diffuse the dopant into the III-N material GaN without decomposing the surface.

Selective area diffusion doping of III-N materials

A hybrid edge termination structure and method of forming the same. The hybrid edge termination structure in accordance with the invention is based on a junction termination extension (JTE) architecture, but includes an additional Layer of guard ring (GR) structures to further implement the implantation of dopants into the structure. The hybrid edge termination structure of the invention has a three-Layer structure, with a top Layer and a bottom Layer each having a constant dopant concentration in the lateral direction, and a middle Layer consisting of a plurality of spatially defined alternating regions that exhibit the electrical properties of either the top or bottom layer. By including the second layer, a discretized varying charge profile can be obtained that approximates the varying charge profile obtained using tapered edge termination but with easier manufacturing and lower cost.

Multi-layer hybrid edge termination for III-N power devices

A light controlled semiconductor switch (LCSS), method of making, and method of using are provided. In embodiments, a vertical LCSS includes: a semiconductor body including a photoactive layer of gallium nitride (GaN) doped with carbon; a first electrode in contact with a first surface of the semiconductor body, the first electrode defining an area through which light energy from at least one light source can impinge on the first surface; and a second electrode in contact with a second surface of the semiconductor body opposed to the first surface, wherein the vertical LCSS is configured to switch from a non-conductive off-state to a conductive on-state when the light energy impinging on the semiconductor body is sufficient to raise electrons within the photoactive layer into a conduction band of the photoactive layer.

Low resistance photoconductive semiconductor switch (PCSS)

Methods for obtaining a free-standing thick (>5 μm) epitaxial material layer or heterostructure stack and for transferring the thick epitaxial layer or stack to an arbitrary substrate. A thick epitaxial layer or heterostructure stack is formed on an engineered substrate, with a sacrificial layer disposed between the epitaxial layer and the engineered substrate. When the sacrificial layer is removed, the epitaxial layer becomes a thick freestanding layer that can be transferred to an arbitrary substrate, with the remaining engineered substrate being reusable for subsequent material layer growth. In an exemplary case, the material layer is a GaN layer and can be selectively bonded to an arbitrary substrate to selectively produce a Ga-polar or an N-polar GaN layer.

Transferring large-area group III-nitride semiconductor material and devices to arbitrary substrates

Light controlled switching modules are provide. In embodiments, a light controlled switching module includes: a housing; a light controlled semiconductor switch mounted to the housing, the light controlled semiconductor switch including a semiconductor body; at least one light source mounted to the housing in a spaced relationship from the light controlled semiconductor switch and positioned to direct light emitted from the at least one light source toward the semiconductor body; and first and second electrodes mounted to the housing and connected to the light controlled semiconductor switch, wherein the first and second electrodes are configured to have variable resistance between the first and the second electrode.

Light controlled switch module

A method for activating implanted dopants and repairing damage to dopant-implanted GaN to form n-type or p-type GaN. A GaN substrate is implanted with n- or p-type ions and is subjected to a high-temperature anneal to activate the implanted dopants and to produce planar n- or p-type doped areas within the GaN having an activated dopant concentration of about 10-10cm. An initial annealing at a temperature at which the GaN is stable at a predetermined process temperature for a predetermined time can be conducted before the high-temperature anneal. A thermally stable cap can be applied to the GaN substrate to suppress nitrogen evolution from the GaN surface during the high-temperature annealing step. The high-temperature annealing can be conducted under Npressure to increase the stability of the GaN. The annealing can be conducted using laser annealing or rapid thermal annealing (RTA).

GaN devices with ion implanted ohmic contacts and method of fabricating devices incorporating the same

A method for growing polycrystalline diamond films having engineered grain growth and microstructure. Grain growth of a polycrystalline diamond film on a substrate is manipulated by growing the diamond on a nanopatterned substrate having features on the order of the initial grain size of the diamond film. By growing the diamond on such nanopatterned substrates, the crystal texture of a polycrystalline diamond film can be engineered to favor the preferred &#x3c;110&#x3e; orientation texture, which in turn enhances the thermal conductivity of the diamond film.

Diamond on nanopatterned substrate

A method for mapping and analyzing a GaN substrate to identify areas of the substrate suitable for fabrication of electronic devices thereon. Raman spectroscopy is performed over the surface of a GaN substrate to produce maps of the Eand Apeaks at a plurality of areas on the substrate surface, the Eand Apeaks being associated with known concentrations of defects and charge carriers, so that areas of the GaN substrate having relatively high resistivity or conductivity which make those areas suitable or unsuitable for fabrication of electronic devices can be identified. The devices can then be fabricated only on suitable areas of the substrate, or the size of the devices can be tailored to maximize the yield of devices fabricated thereon. Substrates not meeting a threshold level of defect and/or charge carrier concentration can be discarded without fabrication of poor-quality devices thereon.

Mapping and evaluating GaN wafers for vertical device applications

Current conducting devices and methods for their formation are disclosed. Described are vertical current devices that include a substrate, an n-type material layer, a plurality of p-type gates, and a source. The n-type material layer disposed on the substrate and includes a current channel. A plurality of p-type gates are disposed on opposite sides of the current channel. A source is disposed on a distal side of the current channel with respect to the substrate. The n-type material layer comprises beta-gallium oxide.

Heterojunction devices and methods for fabricating the same

A high electron mobility transistor (HEMT) and method of producing the same are provided. The HEMT includes a barrier layer formed on a GaN layer. The HEMT also includes a ZrOgate dielectric layer formed by either a ZTB precursor, a TDMA-Zr precursor, or both. The HEMT may also include a recess in the barrier layer in the gate region of the HEMT. The HEMTs may operate in an enhancement mode.

High electron mobility transistors and methods for fabricating the same

A method of growing crystalline materials on two-dimensional inert materials comprising functionalizing a surface of a two-dimensional inert material, growing a nucleation layer on the functionalized surface, and growing a crystalline material. A crystalline material grown on a two-dimensional inert material made from the process comprising functionalizing a surface of a two-dimensional inert material, growing a nucleation layer on the functionalized surface, and growing a crystalline material.

Growth of crystalline materials on two-dimensional inert materials

Growing community of inventors

Alexandria, VA, United States of America

Travis J Anderson