Advanced Micro Devices Corporation

Travis Henry Boraten

David Andrew Werner

Jagadish B Kotra

Michael Warren Boyer

Varun Agrawal

Stuart David Simpson-Biles

A computing device includes a memory having one or more processing-in-memory units, and a host processor that includes one or more caches. The host processor receives a workload that accesses a page of the memory. Further, the host processor dynamically assigns different modes of operation to the page of the memory during different phases of execution of the workload. The different modes are assigned based on whether the workload is to be executed by the host processor, the one or more processing-in-memory units, or the host processor and the one or more processing-in-memory units during the different phases of execution. The host processor processes requests of the workload that access the page of the memory in accordance with the different modes of operation during the different phases of execution. Notably, the different modes of operation specify different caching policies for the page of the memory.

Dynamic caching policies for processing-in-memory

In accordance with the described techniques for condensed coherence directory entries for processing in memory, a computing device includes a core that includes a cache, a memory that includes multiple banks, a coherence directory that includes a condensed entry indicating that data associated with a memory address and the multiple banks is not stored in the cache, and a cache coherence controller. The cache coherence controller receives a processing-in-memory command to the memory address and performs a single lookup in the coherence directory for the processing-in-memory command based on inclusion of the condensed entry in the coherence directory.

Condensed coherence directory entries for processing-in-memory

Selectively bypassing cache directory lookups for processing-in-memory instructions is described. In one example, a system maintains information describing a status—clean or dirty—of a memory address, where a dirty status indicates that the memory address is modified in a cache and thus different than the memory address as represented in system memory. A processing-in-memory request involving the memory address is assigned a cache directory bypass bit based on the status of the memory address. The cache directory bypass bit for a processing-in-memory request controls whether a cache directory lookup is performed after the processing-in-memory request is issued by a processor core and before the processing-in-memory request is executed by a processing-in-memory component.

Bypassing cache directory lookups for processing-in-memory instructions

Various semiconductor chips and chip stack arrangements are disclosed. In one aspect, a semiconductor chip stack is provided that includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a first logic layer and a first semiconductor layer on the first logic layer. The first semiconductor layer has plural first through-silicon transistors operable to selectively control the transmission of data from the first semiconductor chip to the second semiconductor chip and has plural first through-silicon vias to convey control signals to the second semiconductor chip.

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Austin, TX, United States of America

Travis Henry Boraten