National Technology & Engineering Solutions of Sandia, LLC

Travis Forbes

Jesse Moody

Benjamin Thomas Magstadt

Benjamin Magstadt

A programmable delay device providing a delay resolution of less than 1 ns and a maximum delay of >100 ns over a broad bandwidth is disclosed. The device includes an input stage with M sampling switched capacitor elements, reducing the sampling rate by M. The device includes a programmable delay stage with M programmable switched capacitor banks, each bank having N delay switched capacitor storage elements. The programmable delay stage includes a total of M×N delay switched capacitor storage elements, reducing the sampling rate by M×N. This reduced sampling rate permits smaller sampling switches, with reduced leakage current and longer programmable delay times. The device includes an output reconstruction stage that reconstructs a delayed version of the input signal by combining signals from the programmable delay stage. The sampling clocks for the input and output reconstruction stages are independent, allowing a delay resolution corresponding to the sampling rate.

Single clock delay step in multi-stage switched-capacitor delays

A programmable alias delay device providing output in a desired frequency band and a maximum delay of >5 ns over a broad bandwidth and at a high frequency is disclosed. The device includes an input bandpass filter and an input stage with M sampling switched capacitor elements, reducing the sampling rate by M. The device includes a programmable delay stage with M programmable switched capacitor banks, each bank having N delay switched capacitor storage elements, reducing the sampling rate by M×N. This reduced sampling rate permits smaller sampling switches, with reduced leakage current and longer programmable delay times. The device includes an output reconstruction stage that reconstructs a delayed version of the input signal by combining signals from the programmable delay stage. Using a subsequent output alias filter, an alias band in the desired frequency band is selected and output.

Large programmable delay at high frequency through aliasing

An even harmonic multiplier employing complementary current reuse is disclosed. The even harmonic multiplier employs supply voltage and current density scaling to reduce power consumption. Further, by using complimentary NMOS and PMOS transistors, the even harmonic multiplier achieves high areal efficiency. Current reuse causes a reduction in noise at the first harmonic, as the corresponding first harmonic currents from the NMOS and PMOS transistors are in opposite, i.e., canceling, directions. Complementary current reuse is now feasible, as the performance of PMOS transistors at current process nodes is similar to those of NMOS transistors, with appropriate sizing leading to approximately equivalent transconductances. Multiple even harmonic multiplier configurations are possible, with many using transformer circuits at the input and/or the output. The resultant even harmonic multipliers find ready application in millimeter wave radio frequency receivers. The most common even harmonic multiplier is a frequency doubler, which produces a strong second harmonic signal.

Complementary current reuse even harmonic frequency multiplier

A low noise amplifier (LNA) offering one or more of the following benefits: increased gain, reduced power consumption, and/or reduced area, while achieving a similar noise figure, is disclosed. The LNA achieves these benefits by employing an inductorless chip design, current reuse among the transistors, bias sharing, limited AC coupling capacitors, common gate input device feedback, and careful sizing of the transistors.

Miniature ultra-low-power LNA employing current reuse and bias sharing

A programmable delay device that provides delays of more than 100 ns over a broad bandwidth is disclosed. The device includes an input stage that employs M sampling switched capacitor elements such that each sampling switched capacitor element samples at a rate of only 1/M of the fundamental sampling rate. The device includes a programmable delay stage with M programmable switched capacitor banks, each programmable switched capacitor bank having N delay switched capacitor storage elements. Thus, the programmable delay stage includes a total of M&#xd7;N delay switched capacitor storage elements, thereby reducing the sampling rate by a factor of M&#xd7;N. This reduced sampling rate permits much smaller sampling switches, resulting in reduced leakage current and enabling far longer programmable delay times. Lastly, the device includes an output reconstruction stage that reconstructs a delayed version of the input RF signal by combining signals from the programmable delay stage.

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Overland Park, KS, United States of America

Travis Forbes