Lsi Logic Corporation

Lsi Corporation

Agere Systems Inc.

Travis Alister Bradfield

Gregory A Johnson

Robert E Ward

Tracy Robert Spitler

David M Berka

Jeffrey K Whitt

Paul Jeffrey Smith

Andrew Carl Brown

Matthew Richard Motiff

A method of eliminating a runaway condition in a PLL includes the steps of: determining whether the PLL is locked to an input reference signal; when the PLL is not locked to the input reference signal, determining whether a frequency of an output signal generated by the PLL exceeds a prescribed maximum frequency; and when the frequency of the output signal generated by the PLL exceeds the prescribed maximum frequency, resetting the PLL to thereby eliminate the runaway condition.

Configurable reset circuit for a phase-locked loop

An apparatus and method for filtering glitches in data signals are provided. The apparatus and method provide a programmable glitch filter that may be programmed to filter glitches of different depths. The apparatus and method further provide a glitch filter that is programmable and incorporates a synchronizer for synchronizing the filtered output from the glitch filter to a different clock domain than that of the clock input.

Programmable glitch filter

An arbitration elimination scheme for a bus. In a preferred embodiment, a programmable counter determines when a SCSI bus idle condition is reached and when a portion of an arbitration window for the bus has passed without participants. If there are no participants for arbitration, the SCSI initiator eliminates arbitration by asserting SEL and issuing initiator/target IDS. If any other device attempts to arbitrate at this time, the device sees SEL asserted and does not attempt to participate in arbitration.

Method for improving selection performance by using an arbitration elimination scheme in a SCSI topology

A silent mirroring protocol is provided, which eliminates the arbitration/selection times associated with all nexuses after the first nexus. During the initial SCSI bus negotiation, the initiator determines the transfer mode capability of all targets. The initiator establishes a group identification. Participants of the group recognize the group and look for an individual identification within the group. The initiator performs arbitration/selection with attention to the leader of the group. The initiator uses a message out phase with a vendor command to select a participant for a data block transfer. Each participant snoops the bus and recognizes when it is the target. If the initiator has more data to mirror, the process is repeated. When the last data block is transferred, the initiator sends a message out to the last participant, which is interpreted by the target leader as a command to release the bus. Each participant reselects the nexus initiator and returns a status.

Method, apparatus, and program for improving data mirroring performance in a SCSI topology

An innovative circuit is disclosed that enhances performance on a SCSI bus by pipelining nexuses in order to associate all nexus attributes on a per nexus basis. For example, a pipeline of nexuses is created so as to associate all of the nexus attributes from different connections involved. A plurality of load stages is provided whereby each load stage can latch all nexus attributes received at that stage. The latched nexus attributes can be loaded and stored at that stage or shifted to the next stage. As a result of the loading and shifting operations, a pipeline of nexuses is created that associates all of the nexus attributes received from the different connections on a per nexus basis. Therefore, all types of data traffic can be processed concurrently on a SCSI bus, which enhances data throughput and bus performance.

Pipeline SCSI nexus associativity circuit

A system and method for implementing logic changes in integrated circuits (ICs). In a preferred embodiment, donor logic elements are taken from donator logic paths. The donated cells are implemented into a logic path altered by an ECO. The donated cell is replaced by spare cells. Timing analysis is done to ensure all logic paths are timing closed.

System and method for achieving timing closure in fixed placed designs after implementing logic changes

The present invention is a method, system, and product for optimizing timing in a circuit after layout of the circuit has been completed. The circuit includes at least one variable delay line and includes coupled endpoint devices. The variable delay line includes multiple, different selectable settings. A current setting of the variable delay line is varied from a maximum setting to a minimum setting. A timing accuracy indicator of a combination of the coupled endpoint devices is determined as the variable delay line is varied from its maximum setting to its minimum setting. Thus, multiple timing accuracy indicators are determined where an indicator is determined for and associated with each one of the settings from the maximum setting to the minimum setting. An optimum one of the selectable settings is determined utilizing the timing accuracy indicators, wherein the optimum one of the settings is associated with an optimum one of the multiple timing accuracy indicators.

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Colorado Springs, CO, United States of America

Travis Alister Bradfield