Verisilicon Holdings Company Ltd.

Tracy Nguyen

Asheesh Kashyap

Vijayanand Angarai

Michelle Y Che

Introduced herein is a program counter advancing technique that uses NOP padding without its limitations. During a build process, the introduced technique removes EOG markers for instruction groups that are immediately followed by the NOP instructions that are immediately followed by an instruction group beginning at a start of a cache line. As such, during an execution process, when the processing unit detects an absence of an EOG marker in the requested instruction group, it knows that a group of NOP instructions are about to follow and skips over them by directly advancing the program counter to a start of a subsequent cache line where the next instruction group starts. In addition to the presence of an EOG marker, the introduced technique also takes into account whether the requested instruction group is a straddling group when advancing the program counter to a start of the subsequent cache line.

Advancing a program counter to a start of a subsequent cache line based on a straddling group indicator in a current cache line

A prefetch buffer and prefetch method. In one embodiment, the prefetch buffer has a main buffer embodied as a direct-mapped cache, and the prefetch buffer includes: (1) an alias buffer associated with the main buffer and (2) a prefetch controller associated with the main buffer and the alias buffer and operable to cause the alias buffer to store potentially aliasing cachelines of a loop body instead of the main buffer.

Digital signal processor prefetch buffer and method

A next program counter (PC) value generator. The next PC value generator includes a discontinuity decoder that is provide to detect a discontinuity instruction among a plurality of instructions and a tight loop decoder that is provide to: a) detect a tight loop instruction, and b) provide a tight loop instruction target address. The next PC value generator further includes a next PC value logic having a plurality of inputs: a first input coupled to an output of the discontinuity decoder, and a second input coupled to an output of the tight loop decoder. The next PC value logic provides as an output, without a stall, a control signal that a next PC value is to be loaded with the tight loop instruction target address if: the discontinuity decoder detects a discontinuity instruction, and the tight loop decoder detects a tight loop instruction.

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Lewisville, TX, United States of America

Tracy Nguyen