Advanced Micro Devices Corporation

Lsi Corporation

Tracy J Feist

Gerald Robert Talbot

Rajesh Kumar

Milam Paraschou

Edoardo Prete

Jeffrey Cooper

Douglas J Feist

Ethan Crain

Systems, apparatuses, and methods for implementing a combo scheme for direct current (DC) level shifting of signals are disclosed. A receiver circuit receives an input signal on a first interface. The first interface is coupled to a resistor in parallel with a capacitor which passes the input signal to a second interface. Also, the first interface is coupled to a first pair of current sources between ground and a voltage source, and the second interface is coupled to a second pair of current sources between ground and the voltage source. An op-amp drives the current sources based on a difference between a sensed common mode voltage and a reference voltage. Based on this circuit configuration, the receiver circuit is able to prevent baseline wander, perform a DC level shift of the input signal, and achieve linear equalization of the input signal.

Combination scheme for baseline wander, direct current level shifting, and receiver linear equalization for high speed links

Systems, apparatuses, and methods for applying duty cycle correction to a level shifter via a feedback common mode resistor are disclosed. A circuit includes a capacitor, an inverter, and at least one feedback resistor. An input signal is received and coupled through the capacitor to the inverter. To correct for duty cycle distortion on the input signal, a duty cycle correction signal is applied to the at least one feedback resistor in the feedback path. The duty cycle correction signal can be applied as a voltage or as a current. In one implementation, the location of the injection point for applying the duty cycle correction signal within the at least one feedback resistor is programmable.

Application of duty cycle correction to a level shifter via a feedback common mode resistor

Methods and structure for on-chip self-test of clock jitter for an application clock signal generated within an integrated circuit (IC). Features and aspects hereof provide for acquisition of samples of an application clock signal within the IC and counting the number of samples having a predetermined value. The count is compared to acceptable limits range values to generate a pass/fail signal of the IC use by external automated. A sample clock is generated based on the reference clock used by a Phase Locked Loop (PLL) circuit. An incremental delay is added to the sample clock pulse such that the sequence of samples 'walk' through an application clock pulse waveform to sense clock jitter at various points of the waveform based on the counts. Acceptable limits range for the count at each sampled point, the incremental delay, and the number of samples at each delayed value may be user programmed.

Methods and structure for on-chip clock jitter testing and analysis

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Tracy J Feist