Broadcom Corporation

Newport Media, Inc.

Tracy C Denk

Chaoliang T Chen

Steven T Jaffe

Philip Treigherman

James Carwana

Darren Duane Neuman

Brian Francis Schoner

Rajesh Mamidwar

Chengfuh Jeffrey Tang

Greg Alan Kranawetter

Patrick Y Law

Sandeep Bhatia

Iue-Shuenn Chen

Aleksandr M Movshovich

Jason C Demas

Francis Cheung

Brad Albert Delanghe

David A Baer

Jeffrey Scott Putnam

Hoang Nhu

Ut Nguyen

Shawn Val Johnson

James Douglas Sweet

Yao-Hua Tseng

Jeffrey S Bauch

Guang-Ting Shih

David Chao Hua Wu

Brad Grossman

Chuck Monahan

Dan Simon

Sang Van Tran

Hsien-Chih Jim Tseng

Thu T Nguyen

Ben Giese

Lakshman Ramakrishnan

Jeff Tingley

Nabil R Yousef

Keith LaRell Klingler

Jun Tang

Amy Gayle Hundhausen

Erik Berg

Keith LaRell Klinger

A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.

Television functionality on a chip

A multi-chip antenna diversity architecture includes a first receiver chip including a first tuner, and a first demodulator directly connected to the tuner. The first demodulator demodulates the first input signal received from the first tuner. A first power sequencer that controls the first receiver chip, and a first chip ID including a voltage source Vthat indicates the first receiver chip as a slave chip. A second receiver chip includes a second tuner, and a second demodulator directly connected to the second tuner. The second demodulator demodulates the second input signal received from the second tuner. A second diversity combiner directly connected to the second demodulator. A second chip ID includes a voltage source Vthat indicates the second receiver chip as a master chip. A Diversity State Machine (DSM) controls an operating state of the first receiver chip and the second receiver chip that are structurally identical.

Low power, multi-chip diversity architecture

A multi-chip antenna diversity architecture and method includes a first receiver chip that receives a first input signal from a first antenna. The first receiver chip includes a first tuner that amplifies the first input signal, a crystal operatively connected to a first crystal oscillator circuit, and a first crystal oscillator clock buffer that receives a clock signal from the first crystal oscillator circuit. A first demodulator demodulates the input signal received from the first tuner. A second receiver chip receives a second input signal from a second antenna. The second receiver chip includes a second crystal oscillator circuit, a second crystal oscillator clock buffer, a second tuner, and a second demodulator that receives diversity data from the first demodulator. The first crystal oscillator clock buffer drives the clock signal to the second crystal oscillator clock buffer, the second tuner, and the second demodulator of the second receiver chip.

Multi-chip antenna diversity picture-in-picture architecture

A MPE-FEC memory chip and method for use in a DVB-H receiver, wherein the memory chip comprises a TS demux; a RS decoder; a system bus; and a RAM unit adapted to simultaneously interface to the TS demux, the RS decoder, and the system bus through time-multiplexing, wherein the RAM unit is adapted to (i) access multiple-words per clock cycle, and (ii) cache write and read accesses to reduce memory access from the TS demux and the system bus, and wherein the RAM unit is adapted to be clocked at a speed higher than an interfacing data-path to increase an effective throughput of the RAM unit. The RAM unit may comprise multiple RAM sub units, wherein while a first RAM sub unit is clock gated, the remaining multiple RAM sub units are accessible.

Integrated MPE-FEC RAM for DVB-H receivers

All digital RF modulator. An RF modulator, implemented using only digital techniques, obviates the need for an additional board, implemented using discrete analog components, to perform the necessary modulation to provide the RF output signal for use with a display device (television). Modern displays typically include functionality to support a number of input types beyond an RF input. However, older, legacy displays typically only support inputs that are RF in nature. A fully integrated solution that performs the RF modulation of the output signal that may be used in such legacy types systems is provided using digital techniques.

All digital radio frequency modulator

Location cache memory architectures that only require 32 Kbits or less per frame to store erasure information with simple address mapping to the main MPE-FEC RAM for easy column-wise and row-wise access. Alternative architectures are designed to greatly reduce the size and logic complexity of the MPE-FEC erasure cache memory. Two architectures reduce the erasure cache size down to 32 Kbits and 28 Kbits, correspondingly, without introducing additional erasure locations, while another architecture further reduces the required memory size down to 16K, 8K, 4K, or 2K bits with a slight increase in the total erasure locations. All architectures group the data in MPE-FEC frame memory into blocks of 2consecutive bytes and use one or a few bits to store the erasure status in each block, thereby, greatly reducing the required cache memory size.

Compact MPE-FEC erasure location cache memory for DVB-H receiver

Methods and apparatus for reducing precision of an input signal, by comparing a portion of the input signal to a preselected threshold value, and determining a selectable bias responsive to the comparison. By combining a portion of the input signal with the selectable bias, a reduced precision signal, having minimized or eliminated rounding error, is generated. The selectable bias corresponds to a predetermined characteristic of one of bias, an error signal, the input datum, the reduced precision datum, and a combination thereof.

Apparatus and method for reducing precision of data

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Aliso Viejo, CA, United States of America

Tracy C Denk