Intel Corporation

Digital Equipment Corporation

Tracey L Gustafson

Pak-Lung Seto

Victor Lau

Gary Tsao

Nai-Chih Chang

Robert J Safranek

Joel James McCormack

Ramacharan Sundararaman

Christopher C Gianos

James T Claffey

Danny Paul Eggleston

Methods and apparatus relating to techniques for Cross-Die Interface (CDI) snoop and/or go (or completion) message ordering are described. In one embodiment, the order of a snoop message and a completion message are determined based at least on status of two bits. The snoop and completion messages are exchanged between a first integrated circuit die and a second integrated circuit die. The first integrated circuit die and the second integrated circuit die are coupled through a first interface and a second interface and the snoop message and the completion message are exchanged over at least one of the first interface and the second interface. Other embodiments are also disclosed.

Cross-die interface snoop or global observation message ordering

According to one embodiment, an apparatus is disclosed. The apparatus includes a port having a plurality of lanes, a plurality of protocol engines. Each protocol engine is associated with one of the plurality of lanes, and processes tasks to be forwarded to a plurality of remote nodes. The apparatus also includes a first port task scheduler (PTS) to manage the tasks to be forwarded to the one or more of the plurality of protocol engines. The first PTS includes a register to indicate which of the plurality of protocol engines the first PTS is to support.

Method using port task scheduler

Hardware port scheduler (PTS) having register to indicate which of plurality of protocol engines PTS is to support

The invention includes an apparatus and method for buffering data transmitted by a processor and received by an I/O device via a memory and buses. The memory arranged at a plurality of levels includes a lower level of the memory operating faster than a higher level of the memory. A plurality of ring buffers are allocated at different levels of the memory and available buffers at a lowest possible level of the memory are preferentially selected as write buffers to store data transmitted by the processor. The apparatus includes a first level of the memory arranged on an integrated circuit with the processor, a second level of the memory arranged in an off-chip cache, and a third level of the memory arranged in a dynamic random access memory. Read buffers are selected to store data to be received by the I/O device. Stored control values indicate the order for selecting the read buffers and are used by the processor to select the write buffer. Control values are stored in sets of registers located in the I/O device and in a software-based set of registers located in the dynamic random access memory. A selection register located in the I/O device indicates the selected read buffer.

Hierarchical ring buffers for buffering data between processor and I/O

Growing community of inventors

Hudson, MA, United States of America

Tracey L Gustafson