Texas Instruments Corporation

Other

Texas Instruments Incorpated

Trace Quentin Hurd

Deborah J Riley

Antonio Luis Pacheco Rotondaro

Antonio L P Rotondaro

Lindsey H Hall

Phillip D Matz

Elisabeth Marley Koontz

Scott Robert Summerfelt

Luigi Colombo

Sanjeev Aggarwal

Laura Wills Mirkarimi

Stephen Roy Gilbert

Changming Jin

Stephanie Watts Butler

Peijun Chen

Sue E Crank

Sameer Kumar Ajmera

Majid Movahed Mansoori

ChangFeng F Xia

Shirin Siddiqui

A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure.

Semiconductor device with gate-undercutting recessed region

The present invention provides a method for manufacturing an integrated circuit. In one embodiment, the method includes etching one or more openings within a substrate using an etch tool, and subjecting the one or more openings to a post-etch clean, wherein a delay time exists between removing the substrate from the etch tool and the subjecting the one or more opening to the post-etch clean. This method may further include exposing the substrate having been subjected to the post-etch clean to a rinsing agent, wherein a resistivity of the rinsing agent is selected based upon the delay time.

Method for using a modified post-etch clean rinsing agent

A semiconductor device comprising a gate structure on a semiconductor substrate and a recessed-region in the semiconductor substrate. The recessed-region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure.

Crystallographic preferential etch to define a recessed-region for epitaxial growth

The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer () over a gate dielectric layer () located on a substrate (), and patterning the gate electrode layer () using a combination of a dry etch process () and a wet etch process ().

Multi-step process for patterning a metal gate electrode

The present invention provides a process of manufacturing a semiconductor devicewhile reducing silicon loss. In one aspect, the process includes removing a photoresist layerfrom a semiconductor substrateadjacent a gateand cleaning the semiconductor substrate with a wet clean solution. The removing step includes subjecting the photoresist layerto a plasma ash. The plasma ash removes at least a portion of a crustformed on the photoresist layerbut leaves a substantial portion of the photoresist layer. The photoresist layeris subjected to a wet etch subsequent to the plasma ash that removes a substantial portion of the photoresist layer

Silicon recess improvement through improved post implant resist removal and cleans

The present invention provides a system () for remediating aberrations along the perimeter of a semiconductor wafer (). The system includes a cleaning apparatus () within which the wafer is spun within a confined area. A chuck () defines the confined area, having a sidewall that extends above the upper surface () of the wafer and surrounds the perimeter of the wafer. The chuck also has a bottom wall, with an aperture formed therein, beneath the wafer. The system includes an isolation barrier (), disposed atop the bottom wall of the chuck and around the aperture, in proximity to the lower surface so of the wafer. This forms a narrow gap () between the barrier and the wafer. A pressurized source forcefully directs a gas () at and along the lower surface of the wafer. The system also includes a remediation solution () that is applied to the upper surface of the wafer. The solution is forced into a well () formed between the chuck sidewall and the perimeter of the wafer, such that the solution bathes the perimeter of the wafer.

Versatile system for wafer edge remediation

A method of preparing a die comprises treating exposed silicon to form an oxide prior to silicide formation; and depositing metal on the oxide. The metal may comprise titanium, cobalt, nickel, platinum, palladium, tungsten, molybdenum, or combinations thereof on the oxide. The oxide may be less than or equal to about 15 angstroms thick. In various embodiments, treating exposed silicon to form an oxide comprises forming a non-thermal oxide. Treating exposed silicon to form an oxide may also comprise treating the exposed silicon with an oxidizing plasma; alternatively, treating exposed silicon to form an oxide may comprise forming a chemical oxide. In certain other embodiments, treating exposed silicon to form an oxide comprises treating exposed silicon with a solution comprising ammonium hydroxide, hydrogen peroxide, and water; hydrochloric acid, hydrogen peroxide, and water; hydrogen peroxide; ozone; ozonated deionized water; or combinations thereof.

Treatment of silicon prior to nickel silicide formation

A trench and via structure is formed in a low k dielectric layer () formed over a silicon substrate (). Super critical COand a first silylization agent are used to form a chemically bonded high density surface layer (). Silanol species are removed from the low k dielectric layer () using super critical COand a second silylization agent. A barrier layer () and copper () are used to fill the trench and via structure.

Method to reduce silanol and improve barrier properties in low k dielectric ic interconnects

The present invention provides, in one embodiment, a method of forming a copper layer () over a semiconductor substrate (). The method comprises coating a copper seed layer () located over a semiconductor substrate with a protective agent () to form a protective layer (). The method also includes placing the semiconductor substrate in an acid bath () to remove the protective layer. The method further includes electrochemically depositing a second copper layer () on the copper seed layer. Such methods and resulting conductive structures thereof may be advantageously used in methods to manufacture integrated circuits comprising copper interconnects.

Surface treatment of copper to improve interconnect formation

Methods are presented for fabricating MOS transistors, in which a sacrificial material such as silicon germanium is formed over a gate contact material prior to gate patterning. The sacrificial material is then removed following sidewall spacer formation to provide a recess at the top of the gate structure. The recess provides space for optional epitaxial silicon formation and suicide formation over the gate contact material without overflowing the tops of the sidewall spacers to minimize shorting between the gate and the source/drains in the finished transistor.

Methods for fabricating transistor gate structures

A ferroelectric device fabrication process is described in which ferroelectric device contaminant substances (e.g., Pb, Zr, Ti, and Ir) that are incompatible with standard CMOS fabrication processes are tightly controlled. In particular, specific etch chemistries have been developed to remove incompatible substances from the backside and edge surfaces of the substrate after a ferroelectric device has been formed. In addition, a sacrificial layer may be disposed over the bottom and edge surfaces (and, in some embodiments, the frontside edge exclusion zone surface) of the substrate to assist in the removal of difficult-to-etch contaminants (e.g., Ir). In this way, the ferroelectric device fabrication process may be integrated with a standard semiconductor fabrication process, whereby ferroelectric devices may be formed together with semiconductor integrated circuits without substantial risk of cross-contamination through shared equipment (e.g., steppers, metrology tools, and the like).

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Plano, TX, United States of America

Trace Quentin Hurd