Hitachi, Ltd.

Hitachi Tohbu Semiconductor, Ltd.

Toyomasa Koda

Masatoshi Kimura

Isao Yoshida

Takashi Yamaguchi

Ichiro Imaizumi

Masayoshi Yoshimura

Shikayuki Ochi

Kouzou Sakamoto

Takeaki Okabe

Akio Hoshi

Yukihiro Sato

Shigeo Ohtaka

Kazuo Hoya

Kouichiro Satonaka

A packaged semiconductor device has, according to one embodiment of the present invention, a semiconductor pellet having an electronic circuit therein and electrode pads formed on a principal surface of the pellet, a plurality of electrical connection bumps provided on the electrode pads, a plurality of heat dissipation bumps provided at the principal surface of the pellet and electrically insulated from the electronic circuit and the electrode pads, electrical connection leads for the electronic circuit, heat dissipators for the electronic circuit and a packaging material for sealing pellet, the electrical connection bumps, the heat dissipation bumps and parts of the electrical connection leads and the heat dissipator. One or more of the heat dissipation bumps are arranged relatively nearer to the electronic circuit than the electrical connection bumps for thermal coupling to the electronic circuit. One or more of the electrical connection leads may be engaged with the electrical connection bumps and the heat dissipation bumps and/or one or more of the dissipators may be engaged with the heat dissipation bumps and the electrical connection bumps, thereby serving to effect electrical connection to and heat dissipation for the electronic circuit.

Packaged semiconductor device having heat dissipation/electrical

A method of fabricating semiconductor devices which include vertical elements and control elements. A well is formed by etching in a semiconductor substrate of a first conductivity type, and a first epitaxial layer having a second conductivity type opposite to the first conductivity type is epitaxially grown, followed by etching and/or grinding and/or polishing to fill said well. Further, a second epitaxial layer of the first conductivity type is epitaxially grown on the substrate and on the first epitaxial layer, and an impurity-doped layer of the second conductivity type for isolation is formed in the second epitaxial layer to penetrate therethrough. A first element is formed in the second epitaxial layer in a portion that corresponds to the well, and a second element having a vertical structure and having a current capability higher than that of the first element is formed except a portion of the second epitaxial layer that corresponds to the well.

Method of fabricating semiconductor devices which include vertical

A high-breakdown-voltage semiconductor device wherein a resistor body made of a P-type impurity region is disposed in a surface region of an N-type semiconductor body so as to form a resistor element, a P-type low doped region is disposed around the resistor body, and a plate layer which extends from a high potential electrode of the resistor body covers a main part of the P-type low doped region.

High-breakdown-voltage semiconductor device

A high-breakdown-voltage resistance element comprises a semiconductor body, an impurity layer disposed in a surface region of the semiconductor body to provide a resistor body, a first electrode connected to one end of the resistor body through a contact hole in a first insulating film formed on the surface of the semiconductor body, and a second electrode connected to the other end of the resistor body through another contact hole in the insulating film. A second insulating film is formed on the first and second electrodes, and a third electrode is connected to the first electrode through a contact hole in the second insulating film, so that the entire surface of the resistor body and adjacent areas are covered with the first, second and third electrodes.

High-breakdown-voltage resistance element for integrated circuit with a

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Takasaki, Japan

Toyomasa Koda