Fujitsu Microelectronics Limited

Fujitsu Corporation

Toyoki Suzuki

Mitsuaki Tomida

Osamu Uno

Masahiro Iwamoto

Shuuichi Nagaya

A buffer circuit permitting an input signal to pass and prohibiting the input signal from passing corresponding to an output control signal, including an output switching device, a control portion having a first switching circuit controlling the output switching device into conductive state and a second switching circuit controlling the output switching device into non-conductive state, and controlling the output switching device into the conductive state or non-conductive state corresponding to the input signal and the output control signal, wherein a connecting point between the first switching circuit and the second switching circuit is coupled to the output switching device, and a changing portion connected to the second switching circuit in series and limiting the drive capacity of the output switching device when the output control signal is in an output prohibition state of prohibiting the input signal from passing.

Buffer Circuit and control method thereof

A tolerant input circuit that functions stably regardless of fabrication differences without having to adjust the threshold value of an input circuit. The tolerant input circuit includes a step-down device configured by an N-channel MOS transistor connected between an input pad and the input circuit. Voltage from a power supply is supplied to the gate of the N-channel MOS transistor in the step-down device to decrease the voltage of a high voltage signal provided to the input pad to the voltage of the power supply or lower. The signal with decreased voltage is provided to the input circuit. The tolerant input circuit includes a back gate voltage control circuit for increasing back gate voltage of the N-channel MOS transistor in the step-down device when the input pad is provided with a high voltage signal.

Tolerant input circuit

There is provided an output buffer circuit which can realize high speed voltage transition of an output signal while generation of noise due to signal transition is suppressed. On the occasion of driving a PMOS transistor P, in the period of the state I, when the NMOS transistor Nand NMOS transistors N, Nare turned ON, voltage of the output stage PMOS gate terminal APis sharply dropped and the PMOS transistor Pis turned ON. While the signal is propagated in the shortest delay time to the circuit of next stage, when the NMOS transistor Nand NMOS transistor Nare turned ON in the state II, disturbance of signal waveform can be suppressed by limiting a through-rate of the voltage drop of the output stage PMOS gate terminal AP. Driving capability of the PMOS transistor Pcan be variably controlled by controlling the bias condition of a control signal APby switching, for every state, the NMOS transistors Nto Nwhich are turned ON.

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Kasugai, Japan

Toyoki Suzuki