Oki Electric Industry Co., Ltd.

Kabushiki Kaisha Toyota Jidoshokki

Oki Semiconductor Co., Ltd.

Sicoxs Corporation

National Institute of Advanced Industrial Science and Technology

Toyokazu Sakata

Motoki Kobayashi

Takamitsu Kawahara

Kuniaki Yagi

Akiyuki Minami

Hidetsugu Uchida

Naoki Hatta

Ko Imaoka

Tomoatsu Makino

Hidenori Inui

Hideki Takagi

Kousuke Hara

Yuuichi Kurashima

Mitsuharu Kato

A method for manufacturing a semiconductor substrate may comprise irradiating a surface of a first semiconductor layer and a surface of a second semiconductor layer with one or more types of first impurity in a vacuum. The method may comprise bonding the surface of the first semiconductor layer and the surface of the second semiconductor layer to each other in the vacuum. The method may comprise applying heat treatment to the semiconductor substrate produced in the bonding. The first impurity may be an inert impurity that does not generate carriers in the first and second semiconductor layers. The heat treatment may be applied such that a width of an in-depth concentration profile of the first impurity contained in the first and second semiconductor layers is narrower after execution of the heat treatment than before the execution of the heat treatment.

Semiconductor substrate and method for manufacturing semiconductor substrate

A technique disclosed herein relates to a manufacturing method for a semiconductor substrate having the bonded interface with high bonding strength without forming an oxide layer at the bonded interface also for the substrate having surface that is hardly planarized. The manufacturing method for the semiconductor substrate may include an amorphous layer formation process in which a first amorphous layer is formed by modifying a surface of a support substrate and a second amorphous layer is formed by modifying a surface of a single-crystalline layer of a semiconductor. The manufacturing method may include a contact process in which the first amorphous layer and the second amorphous layer are contacted with each other. The manufacturing method may include a heat treatment process in which the support substrate and single-crystalline layer are heat-treated with the first amorphous layer and the second amorphous layer being in contact with each other.

Manufacturing method for semiconductor substrate

A method for manufacturing a dual damascene structure includes forming a wiring layer over a substrate, forming an inorganic insulating film over the wiring layer, forming a via hole in the inorganic insulating film using a first resist pattern with an opening as an etching mask, removing the first resist pattern, forming an organic insulating film on the inorganic insulating film and in the via hole, forming a hard mask on the organic insulating film, forming a hard mask pattern using a second resist pattern with an opening on the hard mask as an etching mask, forming a wiring groove by etching the organic insulating film using the second resist pattern and the hard mask pattern as etching masks until the organic insulating film inside the via hole is eliminated and simultaneously eliminating the second resist pattern, and implanting a conductive substance into the via hole and wiring groove.

Method for manufacturing a semiconductor device and method for etching the same

A base substrate is first prepared, and a high dielectric amorphous film composed of a high permittivity material is formed over the base substrate. Next, an amorphous silicon film is formed over the high dielectric amorphous film with an amorphization temperature of the high permittivity material as a deposition temperature. Then, the amorphous silicon film is processed by a photolithography method and dry etching to form gate electrode forming films. Wet etching with the gate electrode forming films as masks is next performed to allow portions of the high dielectric amorphous film, which are covered with the gate electrode forming films to remain and remove exposed portions of the high dielectric amorphous film. Next, the gate electrode forming films are thermally treated to reform amorphous silicon into polysilicon so as to constitute gate electrodes.

Method for manufacturing semiconductor elemental device forming an amorphous high dielectric film and an amorphous silicon film

A method for manufacturing a semiconductor element includes preparing an SOI layer having a transistor forming area and an element isolation area, forming an oxidation-resistant mask layer on the SOI layer, forming a resist mask over the transistor forming area on the oxidation-resistant mask layer, a first etching that etches the oxidation-resistant mask layer using the resist mask so that a predetermined thickness of the oxidation-resistant mask layer remains, a second etching that etches the remaining oxidation-resistant mask layer, using the resist mask and exposing the SOI layer at the element isolation area, and oxidizing the exposed SOI layer using the remaining oxidation-resistant mask layer, to form an element isolation layer. An etching rate during the first etching is higher than during the second etching and a silicon-to-etching selection ratio during the second etching is higher than during the first etching.

Method for manufacturing semiconductor element

An etching method for plasma-etching a low-k film, wherein the plasma etching is conducted under an etching gas atmosphere including a fluorocarbon gas, Ogas and Ar gas, and under the conditions of a pressure of 60 mTorr (7999.32 mPa) or higher and a high-frequency output (RF power) of 600 W or less.

Etching method and semiconductor device fabricating method

This invention provides a semiconductor device that can ensure that stress on the nitride film is not increased or is reduced, and that can prevent an increase in interconnection capacity. The semiconductor device comprises a underlayer, a base oxide film that is formed on this underlayer, a nitride film pattern with a hole pattern that is provided on this base oxide film, holes that penetrate the base oxide film, an upper oxide film provided on the base oxide film to cover the nitride film pattern, wiring grooves provided through the upper oxide film in which part of the nitride film pattern including the hole pattern is exposed, and wiring metal that fills the holes and wiring grooves. The nitride film pattern is formed with such a shape and size that surrounds the outside of the wiring grooves and is separate from neighbouring nitride film patterns.

Semiconductor device with reduced interconnection capacity

The present invention provides an auxiliary semiconductor device fabrication method that forms wiringby using the wiring groovethat is formed in the sacrificial oxide film. An interlayer insulating film is formed by removing, by means of etching, the sacrificial oxide film that is used as a mold for the wiring layer formation and then allowing the porous Low-k film to fill the region from which the sacrificial oxide film has been removed.

Semiconductor device fabrication method

A semiconductor device having conductive paths separated by cavities is formed by depositing organic spin-on glass between the conductive paths, forming gaps between the organic spin-on glass and the conductive paths, and then removing the organic spin-on glass through the gaps. The gaps may be formed as a dummy pattern of via holes that are misaligned with the conductive paths, so that they extend past the upper surfaces of the conductive paths and form fine slits beside the conductive paths. This method of removing the spin-on glass leaves cavities that are free of unwanted oxide residue and debris, thereby minimizing the capacitive coupling between adjacent conductive paths.

Growing community of inventors

Tokyo, Japan

Toyokazu Sakata