Hitachi, Ltd.

Renesas Technology Corp.

Other

Toyokazu Hori

Masaru Hase

Hiroshi Yamada

Norihiko Sugita

Toshihito Habuka

Naoto Inokawa

Hiroshi Nogami

Tetsuya Yamato

Tatsuji Matsuura

Masaki Noda

Kazuaki Hori

Kazuyuki Takada

Nario Sumi

The invention comprises: processing for receiving an OFDM packet having a preamble and the following data transmission symbol, in which packet the subcarrier interval of the preamble is set wider than that of the data transmission symbol; processing for estimating a DC offset occurring at a receiving side by using the received preamble; processing for correcting the DC offset on the received data transmission symbol, according to the estimation result of the DC offset; and processing for demodulating the DC offset corrected data transmission symbol. Thus, it is possible to estimate a DC offset and then correct the DC offset according to the estimated value, in the OFDM packet with no nul symbol defined there.

OFDM demodulation method and semiconductor integrated circuit device

A wireless LAN system has auto gain control with no work load applied to its baseband processing block. When the wireless LAN system gets ready to receive a signal, the gain control circuit switches between the receiving antennas. The gain control circuit sets gain setting value time divisional data according to the level of a received signal to roughly control the gain to be set in the LAN and the gain to be set in two programmable gain amplifiers.

Semiconductor integrated circuit device, wireless LAN system, and auto gain control system

A bus arbitration apparatus for an image processing processor is operable such that when a channel having a high necessity of a real-time processing operation issues a bus use request, a bus use permission is not given to another channel having a low necessity of a real-time processing operation. The bus arbitrator of the data includes a timer for counting down use permission time with respect to the channel having the high necessity of the real-time processing operation, and a register for the channel having the low necessity of the real-time processing operation. A value larger than a maximum value of the timer is set to the value of the register. In the bus arbitration, the value of the register is compared with that of the timer, and then the bus use permission is given to a channel having the small value.

Data processing processor

One multiplier,operated at a normalized frequency,is provided to multiply the elements of DCT transformation coefficients and the elements of input data, and the multiplication results are added by a cumulative adder,to determine cumulative addition results corresponding to the sum (x,&plus;x,) and the difference (x,&minus;x,) of a pair of elements (x,x,) of data to be outputted from a one-dimensional DCT operation circuit,The paired cumulative addition results are added and subtracted by an adder,and a subtracter,respectively, to determine the elements (x,x,). The operations are performed specific times the number of which is one half of the number of elements of a column of the matrix of the input data to determine the elements of a column of the matrix of the output data and are performed specific times the number of which is equal to the number of elements of a row of the matrix or the input data to determine all the elements of the matrix of the output data. As a result, the scale of the DCT operation circuit is reduced, thereby reducing the power consumption.

Discrete cosine transformation operation circuit

Growing community of inventors

Kodaira, Japan

Toyokazu Hori