Matsushita Electric Industrial Co., Ltd.

Matsushita Electronics Corporation

Toyokazu Fujii

Yasushi Naito

Kazuhiko Hashimoto

Mikio Nishio

Mitsuru Sekiguchi

Takatoshi Yasui

Hiroshi Yamamoto

Shinichi Imai

Tsutomu Fujita

Ichiro Nakao

Yuka Terai

Chiaki Kudo

A DRAM cell transistor formed on a silicon substrate comprises a first BPSG film, a silicon oxide film as a supporting film laid thereover, a storage node including a contact portion filling a contact hole extended through the silicon oxide film and the first BPSG film, an oxidized silicon nitride film as a capacitor insulating film, and a plate electrode. There may be further provided a second BPSG film thereover. Even if the first BPSG film at a lower level is caused to reflow by a process for oxidizing the silicon nitride film for formation of the oxidized silicon nitride film as the capacitor insulating film or a process for ref lowing the second BPSG film, the silicon oxide film as the supporting film applies to the capacitor insulating film a stress against the deformation thereof and hence, the oxidized silicon nitride film free from wrinkle or cracks is provided as the capacitor insulating film. Thus, a semiconductor device free from wrinkle or cracks in the nitride film associated with thermal history and a process for fabrication of the same can be offered, even though the nitride film is laid over the insulating film having a reflowable property.

Process for fabrication of a dram cell having a stacked capacitor

On a semiconductor substrate, chips to be products and alignment chips located at a portion a part thereof is left out from a peripheral part of the semiconductor substrate are formed. Contact holes and alignment marks are formed at the chips to be products and the alignment chips. Covering the alignment chips with alignment mark cover parts of a substrate holder, a material for metal wiring is deposited on the semiconductor substrate to form a metal film on the substrate. A mask pattern is formed on the metal film using the alignment marks of the alignment chips on which the metal film is not formed.

Alignment chips positioned in the peripheral part of the semiconductor

In a metal silicide film, excessive silicon is contained and precipitated in silicide grain boundaries thereof. The thus precipitated excessive silicon makes a diffusion path of impurities, which extends along WSi.sub.2 grain interfaces, discontinuous in the metal silicide film. As a result, the impurities do not diffuse laterally in the metal silicide film even after a heat treatment is performed.

Semiconductor device with particular metal silicide film

A method for fabricating a semiconductor device which includes a metal silicide film for electrically connecting a first silicon region containing a p-type impurity with a second silicon region containing an n-type impurity is disclosed. The method includes the step of depositing the metal silicide film so as to contain excessive silicon. Such excessive silicon is precipitated in silicide grain boundaries in the metal silicide film and thus makes a diffusion path of impurities along the silicide grain boundaries discontinuous.

Method for fabricating semiconductor device containing excessive silicon

A semiconductor device comprising a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a polycide film including a polysilicon layer and a silicide layer formed on the insulating film. The polysilicon layer includes a p-type region having p-type impurities diffused therein and an n-type region having n-type impurities diffused therein. The p-type impurities are implanted into the silicide layer in order to have a substantially uniform concentration over the entire portion thereof, so that the p-type impurities in the p-type region of the polysilicon layer do not diffuse into the silicide film by a post heat treatment.

Method for fabricating a semiconductor device comprising a polycide

Metal film deposition apparatus and metal film deposition method

A semiconductor device comprising a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a polycide film including a polysilicon layer and a silicide layer formed on the insulating film. The polysilicon layer includes a p-type region having p-type impurities diffused therein and an n-type region having n-type impurities diffused therein. The p-type impurities are implanted into the silicide layer in order to have a substantially uniform concentration over the entire potion thereof, so that the p-type impurities in the p-type region of the polysilicon layer do not diffuse into the silicide film by a poet heat treatment.

Semiconductor device with a dual type polycide layer comprising a

A semiconductor device of the present invention includes a semiconductor substrate, a p-type impurity diffused region formed in the semiconductor substrate, and a polycide interconnection electrically connected to the p-type impurity diffused region. In the semiconductor device, the polycide interconnection includes a first polysilicon film, a refractory metal silicide film formed on the first polysilicon film, and a second polysilicon film formed on the refractory metal silicide film.

Semiconductor device and a method of fabricating the same

Described is a method for manufacturing semiconductor devices which includes a heat treating process for heating and cooling semiconductor substrates mounted on a boat at a predetermined pitch according to a predetermined temperature profile, in order to flatten the surface of each semiconductor substrate by reflowing an insulating film containing impurities, for example, a BPSG film formed on the substrate. In the heat treating process, one of the control factors which affects the formation of grains or particles due to the impurities contained in the insulating film is set so as to prevent the impurities from generating grains or particles during the heat treatment. Also disclosed is a method of preventing the generation of grains or particles by widening the pitch of the mounted substrates.

Method for manufacturing a semiconductor device using a heat treatment

A semiconductor device has a multilayered metalization including a CVD tungsten film, a thin buffer layer deposited on the CVD tungsten film by sputtering, and an Al-alloy layer formed on the buffer layer. Due to the existence of the thin buffer layer, the crystal grains of the Al-alloy layer do not become small and the electromigration resistance as wiring is enhanced.

Semiconductor device and method of fabricating the same

In a CVD contact formed on a shallow junction having a depth of 0.2 micron or less, the presence of aluminum generates a leakage current at the junction after heat treatment. In order to restrain the leakage current, a barrier metal is formed below the aluminum electrode to form an Al/barrier metal/CVDW (tungsten) structure. A contact free from junction leakage and having a high aspect ratio is thereby realized.

Growing community of inventors

Moriguchi, Japan

Toyokazu Fujii