Nec Corporation

Renesas Electronics Corporation

Toyoji Yamamoto

Kiyoshi Takeuchi

Tohru Mogami

Koji Watanabe

Toru Tatsumi

Hisashi Takemura

Hitoshi Wakabayashi

Risho Koh

Atsushi Ogura

Nobuyuki Ikarashi

Toshiharu Nagumo

Yukishige Saito

Mitsuhiro Togo

Yukinori Ochiai

Haruhiko Ono

Kazutoshi Shiba

Shigeharu Yamagami

Mitsuru Narihiro

Kohichi Arai

Jong-Wook Lee

Disclosed is a semiconductor device that reduces the area of a transistor in a ReRAM. A plurality of memory cells differ from each other in the combination of bit line and plate line. The potential of plate line PLis a forming voltage. By contrast, the potentials of the other plate lines are +Vi. The potential of bit line BLis 0 V (ground potential). By contrast, the potentials of the other bit lines are +Vi. The potential of is +Vgf. By contrast, the potentials of the other word lines are +Vi.

Semiconductor device and forming method

A semiconductor device includes a semiconductor layer formed on an insulator, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film and extending in a first direction, source/drain regions formed in the semiconductor layer on both sides of the gate electrode, a body contact region in the semiconductor layer, a partial isolating region in which a field insulating film thicker than the gate insulating film intervenes between the semiconductor layer and an extending portion of the gate electrode, and a full isolating region in which the semiconductor layer on the insulator is removed. The full isolating region is formed to be in contact with at least a part of a side parallel to the first direction of the source/drain regions.

SOI MOSFET

A MIS transistor has a gate insulating film made of silicon oxynitride and having a specific dielectric constant which is larger than the expected specific dielectric constant calculated based on a weighted average of the specific dielectric constants based on the weight ratio of the silicon oxide and the silicon nitride contained in the silicon oxynitride film. The gate insulating film having a smaller thickness prevents impurities in the overlying gate electrode from penetrating through the gate insulating film to degrade the silicon substrate.

Semiconductor device including a MIS transistor

Using a lamination of a tungsten silicide layer and a non-doped polysilicon layer as a mask, a dopant impurity is ion implanted into a semiconductor substrate so as to form impurity regions and dope the tungsten silicide layer with the dopant impurity, and the dopant impurity is diffused from the tungsten silicide layer into the non-doped polysilicon layer during the activation of the dopant impurity introduced into the substrate, thereby making the process simple.

Process of fabricating semiconductor device having gate structure doped

Growing community of inventors

Tokyo, Japan

Toyoji Yamamoto