Texas Instruments Corporation

Towfique Haider

Walter Heinrich Demmer

Feng Ying

Jason Meiners

Kazunobu Shin

Bart DeCanne

Walter H Demmer

A data synchronizer that receives an input stream of asynchronous digital data in packets, and provides an output stream of synchronous data in packets. The synchronizer includes a first memory unit and a second memory unit, each having a data input, a data output, a write clock input and a read clock input. A first switch is provided for switching connection of the input in alternating manner between the first memory unit input and the second memory unit input, and a second switch is provided for switching connection of the data synchronizer output in alternating manner between the first memory unit output and the second memory unit output. A write clock is provided to write clock inputs of the first and second memory units. The average data rate of the received valid data during the reception of the packet is determined, and a read clock is generated and provided to the first and second memory units at a rate corresponding to the average data rate of the received valid data bits during the reception of the packet being read. The switching of the first and second switches is controlled such that the switches switch between adjacent packets, with the second switch switching in opposite phase to that of the first switch.

MPEG-2 transport stream packet synchronizer

This invention samples and transmits the CEA-909 standard smart antenna analog pulse train waveforms using only a digital I/O pin for both mode A and mode B operation. This invention implements the smart antenna interface based on a single digital programmable counter. This counter is programmable so that it can tolerate or produce wide variation of symbol width.

Smart antenna interface using only digital I/O supporting both mode A and mode B antenna operation as per CEA 909 standard using a single digital counter

A video decoder (). The decoder comprises an interface () for receiving a set of an integer number S of analog input signals at a same time. The decoder also comprises circuitry for processing the S analog input signals, and that circuitry comprises an integer number N of analog-to-digital converters () for producing a set of the integer number S of digital signals. Each digital signal in the set of S of digital signals corresponds to a respective different one of the S analog input signal, and N is less than S. The decoder also comprises output circuitry (), coupled to the circuitry for processing, for providing each digital signal in the set of S of digital signals to a different respective output conductor.

Video decoder with different signal types processed by common analog-to-digital converter

A video correction system and method are disclosed that provide video correction for an input signal. The system includes a logarithmic converter that creates a logarithmic representation of the input signal. A configurable corrector/converter comprises a plurality of associated components operative to process the logarithmic representation of the input signal. The configurable corrector/converter produces an output signal having at least one desirable signal characteristic. A switch control selects a configuration for the corrector/converter. The configuration indicates at least one of the plurality of associated components that will process the logarithmic representation.

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Allen, TX, United States of America

Towfique Haider