Matsushita Electric Industrial Co., Ltd.

Touru Kakiage

Masato Suzuki

Yoshiaki Kasuga

Yuichi Hashimoto

Jyunichi Yasui

A method of transferring data through a bus includes the steps of: occupying the bus by a first device serving as a bus master; transferring a first predetermined number of data items of all data items to be transferred while the first device is occupying the bus; determining if the first predetermined number of data items have been transferred; determining if the first device should release the bus based on whether or not there is a request from a second device after it is determined that the first predetermined number of data items have been transferred; and releasing the bus by the first deice when it is determined that the first device should release the bus.

Apparatus and method of partially transferring data through bus and bus master control device

A method of transferring data through a bus includes the steps of: occupying the bus by a first device serving as a bus master; transferring a first predetermined number of data items of all data items to be transferred while the first device is occupying the bus; determining if the first predetermined number of data items have been transferred; determining if the first device should release the bus based on whether or not there is a request from a second device after it is determined that the first predetermined number of data items have been transferred; and releasing the bus by the first device when it is determined that the first device should release the bus.

Apparatus and method of partially transferring data through bus and bus

An information processing apparatus includes an instruction storage for storing a plurality of instructions and a central processing unit for fetching the instructions from the instruction storage device so as to execute the instructions. The central processing unit executes a process to perform operations which require at least two machine cycles of the central processing unit by separately executing a first instruction for setting first data required for operations and a second instruction for fetching second data obtained by the operations. The machine cycle is a time unit for executing an instruction by the central processing unit. The central processing unit executes at least one third instruction after executing the first instruction and before executing the second instruction, the third instruction not requiring the second data.

Information processing apparatus and method, and scheduling device for

A bus controller controls an access to a bus connected to a first device which operates in synchronization with a first clock signal and a second device which operates in asynchronization with the first clock signal. The controller includes a detector. The detector receives an access request from a central processing unit which operates in synchronization with a second clock signal different from the first clock signal to detect whether the access request represents an access to the first device or an access to the second device. The controller further includes an access controlling signal generator. The access controlling signal generator generates a first access controlling signal for controlling an access of the first device to the bus in synchronization with the first clock signal and for supplying the first access controlling signal to the first device, in a case where the access request represents the access to the first device. The access controlling signal generator generates a second access controlling signal for controlling an access of the second device to the bus in synchronization with the second clock signal and for supplying the second access controlling signal to the second device, in a case where the access request represents the access to the second device.

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Neyagawa, Japan

Touru Kakiage