Hitachi, Ltd.

Tositada Netsu

Kenichi Kasai

Mitugu Shirai

Hideki Watanabe

Osamu Yamada

Masahide Harada

Yutaka Watanabe

Hideaki Sasaki

Kenji Takeda

Hiroshi Hasegawa

Fumiyuki Kobayashi

Ryohei Satoh

Koichi Sugimoto

Hidetaka Shigi

Masakazu Yamamoto

Tsutomu Imai

Takeshi Yamaguchi

Kiyoshi Matsui

Takaji Takenaka

Mitsunori Tamura

Mitsukiyo Tani

Satoru Ezaki

Takeshi Yano

Hiroyuki Hidaka

Tosaku Kojima

Fumio Imahashi

A circuit board is provided with blind connection vias which are filled with solder. The end portions of the pins of an electronic component are inserted into the connection vias, and are connected to the connection vias by solder. The electronic component is surface mounted on the circuit board with the major portions of the pins exposed.

Surface mounting structure

There is disclosed a multichip module having a sealing-cooling structure which achieves a high packaging density, high sealing-connection reliability, a low manufacturing cost and a high cooling ability. A frame 15, conforming in thermal expansion coefficient to a substrate 11, is soldered at one surface thereof to that surface of the substrate 11 on which semiconductor devices 12 are mounted. The frame 15 is fastened or fixedly secured at the other surface thereof to a lid member 17 by bolts 10 or means without any heat treatment of the whole of the module.

Multichip module with heat sink and attachment means

The present invention provides a multistep electronic circuit device comprising a plurality of parts and elements mechanically or electrically bonded in sequence to each other and to a substrate with a plurality of solders, which comprises as the parts and elements the substrate, input and output pins and LSI chips, and optionally packages and a cooler bonded through multistep bonding, the bondings of the parts and elements including at least one CCB bonding and at least one sealing, the solders each having a lower melting point than the heatproof temperature of the part or element to be bonded with the solder, and one of the solders having a melting point of at least 10.degree. C. lower than that of the other solder used at the bonding step immediately before. The solders used are selected from Au10-15wt%Ge alloy (melting point: 356.degree.-450.degree. C.), Pb1-5wt%Sn alloy (melting point: 314.degree.-325.degree. C.), Pb10-13wt%Sn alloy (melting point: 270.degree.-300.degree. C.), Au20wt%Sn alloy (melting point: 280.degree. C.), Sn3-6wt%Sb alloy (melting point: 232.degree.-243.degree. C.), Sn2-8wt%Ag alloy (melting point: 221.degree.-235.degree. C.), Sn35-55wt%Pb alloy (melting point: 183.degree. -200.degree. C.) and Sn45wt%Pb18wt%Bi (melting point: 135.degree.-160.degree. C.).

Electronic circuit device and method of producing the same

In a pin grid array type multi-chip module structure comprised of a ceramic multi-layer wiring board having the top surface on which a plurality of semiconductor devices are carried, divisional board areas each having the same size are respectively allotted to individual semiconductor devices of the same type. Within respective divisional board areas, the positional relation between the array arrangement of connecting pads on the top surface for connection to the semiconductor devices and the array arrangement of I/O pins on the bottom surface of the board is so determined as to be constant. Metallized patterns inside the board which are to be connected power supply I/O pins and ground I/O pins are made constant for respective divisional board areas allotted to individual semiconductor devices of the same type.

Multi-chip module structure

The invention relates to joining of fine wires, and more particularly to a wire bonding method suitable for connecting a number of wires within a narrow area. A first wire is bonded on a pad, and a second wire is bonded on the position where the first wire has been bonded. Bonding of a subsequent wire is performed in that the wire is stacked and bonded in similar manner mentioned above. Thus a plurality of repair wires can be bonded within one pad even if the pad area is very small.

Wire stacked bonding method

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Hadano, Japan

Tositada Netsu