Fujitsu Corporation

Fujitsu Semiconductor Limited

Toshiyuki Uetake

Yasuhiko Maki

Takako Kagiwata

A semiconductor storage device includes a first cell array including a plurality of memory cells that are connected to a first word line and each of which is connected to each member of a first pair of bit lines. The semiconductor storage device also includes a second cell array including a plurality of memory cells that are connected to a second word line and each of which is connected to each member of a second pair of bit lines. The semiconductor storage device further includes a redundant cell array including a plurality of memory cells that are connected to a word line different from the first and the second word lines and each of which is connected to one member of the first pair of bit lines and to one member of the second pair of bit lines.

Semiconductor storage device

A semiconductor memory device includes memory cells, word lines connected to the memory cells, word driver circuits for driving the word lines, a decoder circuit group including a plurality of decoder circuits outputting a decoder signal for selecting at least one of the word driver circuits, decoder lines connecting the decoder circuits to the word driver circuits, and an equalizing circuit for electrically disconnecting the decoder lines from the decoder circuits and equalizing the voltages of the decoder lines connected to the decoder circuits belonging to the decoder circuit group.

Semiconductor memory device

A semiconductor memory including a sense amplifier circuit for reading the data stored in memory cells and particularly to a semiconductor memory including a self-timing circuit for improving margin for reading data by controlling activation timing of the sense amplifier drive signal in accordance with characteristics of internal memory cells.

Semiconductor memory including self-timing circuit

A semiconductor memory device includes a memory cell array, a decoder circuit configured to assert a decoding signal for selecting an access position in the memory cell array in response to an address signal supplied from an exterior, and a first circuit configured to put the decoding signal of the decoder circuit in an asserted state regardless of a value of the address signal in response to assertion of a standby signal supplied from the exterior.

Semiconductor memory device with reduced leak current

Memory cells, word lines and bit lines are formed on the substrate. Each word line is connected to some memory cells. The bit line is disposed in a wiring layer above the word lines, the bit line being connected to some memory cells and applied with a signal read from the memory cell selected by the word lines. Signal wiring lines are disposed in a wiring layer above the bit lines and partially superposed upon the bit lines. A shield layer is disposed in a wiring layer between the bit lines and signal wiring lines. As viewed along a direction vertical to the surface of the semiconductor substrate, the shield layer includes the bit lines in an area including an area where the bit lines and signal wiring lines are superposed upon each other, openings being formed through the shield layer in areas where the bit lines are not disposed.

Semiconductor storage device with signal wiring lines RMED above memory cells

A decoder circuit includes a detecting device which detects a selecting signal for selecting the decoder circuit, a clock-signal supplying device which supplies a clock signal, and a decoded signal outputting device which outputs a decoded signal according to timing of the clock signal when the detecting device detects the selecting signal.

Growing community of inventors

Kawasaki, Japan

Toshiyuki Uetake