Nec Electronics Corporation

Renesas Electronics Corporation

Nec Corporation

Toshiyuki Takewaki

Koichi Ohto

Daisuke Oshida

Manabu Iguchi

Hironobu Miyamoto

Takuji Onuma

Tatsuya Usami

Yasuhiro Okamoto

Tatsuo Nakayama

Noriaki Oda

Hiroyuki Kunishima

Nobuyuki Yamanishi

Yoshihisa Matsubara

Hiroshi Kawaguchi

Takashi Inoue

Takayuki Nagai

Yoshinao Miura

Yasuaki Tsuchiya

Masayuki Hiroi

Toshiji Taiji

Mieko Hasegawa

Nobuhiro Nagura

Hironori Toyoshima

Hiroaki Nanba

Ichiro Honma

Takaharu Kunugi

Kazuyoshi Ueno

Yorinobu Kunimune

Nobuo Hironaga

Mari Watanabe

Yoshiaki Yamamoto

Hidemitsu Aoki

Hiroaki Tomimori

Shinji Yokogawa

Takeshi Toda

Kenichi Nakabeppu

A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap wider than a band gap of the first nitride semiconductor layer, a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, a gate electrode placed in the trench over a gate insulating film, and a first electrode and a second electrode formed over the second nitride semiconductor layer on both sides of the gate electrode, respectively.

Semiconductor device and method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer, forming thereover a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer, and thereby forming a stacked body, etching the stacked body with a first film placed over the stacked body and including a first opening portion as a mask to form a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, causing an end portion of the first film to retreat from an end portion of the trench, forming a second film over the first film including the inside of the trench, and forming a gate electrode over the second film.

Method of manufacturing semiconductor device with a multi-layered gate dielectric

The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged in the trench via a gate insulation film, and an insulation film formed over the barrier layer outside the opening region. Then, the insulation film has a lamination structure of a Si-rich silicon nitride film, and a N-rich silicon nitride film situated thereunder. Thus, the upper layer of the insulation film is set as the Si-rich silicon nitride film. This enables the improvement of the breakdown voltage, and further, enables the improvement of the etching resistance. Whereas, the lower layer of the insulation film is set as the N-rich silicon nitride film. This can suppress collapse.

Semiconductor device and a method for manufacturing a semiconductor device

To provide a semiconductor device having improved characteristics. The semiconductor device has a substrate and thereon a buffer layer, a channel layer, a barrier layer, a trench penetrating therethrough and reaching the inside of the channel layer, a gate electrode placed in the trench via a gate insulating film, and drain and source electrodes on the barrier layer on both sides of the gate electrode. The gate insulating film has a first portion made of a first insulating film and extending from the end portion of the trench to the side of the drain electrode and a second portion made of first and second insulating films and placed on the side of the drain electrode relative to the first portion. The on resistance can be reduced by decreasing the thickness of the first portion at the end portion of the trench on the side of the drain electrode.

Semiconductor device with varying thickness of insulating film between electrode and gate electrode and method of manufacturing semiconductor device

A semiconductor device includes a substrate, a buffer layer provided on the substrate, a channel layer provided on the buffer layer, an electron supply layer provided on the channel layer, a first contact hole provided on the electron supply layer, a source electrode that is formed within the first contact hole, and electrically connected to the electron supply layer, a second contact hole provided on the electron supply layer, a drain electrode that is formed within the second contact hole, and electrically connected to the electron supply layer, a gate electrode provided between the source electrode and the drain electrode, a second insulating film that is formed to cover the gate electrode, a strain relaxation film that is formed over the second insulating film above the gate electrode, a third insulating film that is formed to cover the source electrode, the drain electrode, and the strain relaxation film, and an organic film that is formed over the third insulating film.

Semiconductor device

A semiconductor device is provided, which includes a substrate, an insulator film formed over the substrate, and plural metal wirings with different widths containing copper as a main component and an impurity which is different from copper. The plural metal wirings includes a first metal wiring having a concentration profile where the concentration of the impurity metal increases from the center part of the stacking direction to the surface and the second metal wiring having a concentration profile where the concentration of the impurity metal decreases from the bottom surface of the stacking direction to the surface. Moreover, the width of the second metal wiring may be larger than the width of the first metal wiring.

Semiconductor device with high reliability and manufacturing method thereof

The reliability of a power MISFET made of a nitride semiconductor material is improved. A strain relaxation film is disposed between a polyimide film and a gate electrode, to suppress a stress exerted on an electron supply layer and a channel layer from the polyimide film, and suppress a stress strain generated in the electron supply layer and the channel layer. As a result, a change in channel electron concentration in the channel layer is suppressed to prevent a threshold voltage or an on-resistance of the power MISFET from fluctuating.

Semiconductor device including a strain relaxation film

In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.

Semiconductor device having silicon-diffused metal wiring layer and its manufacturing method

A semiconductor device including: a substrate; an insulating film formed over the substrate; a copper interconnect, having a plurality of hillocks formed over the surface thereof, buried in the insulating film; a first insulating interlayer formed over the insulating film and the copper interconnect; a second insulating interlayer formed over the first insulating interlayer; and an electroconductive layer formed over the second insulating interlayer, wherein the top surface of at least one hillock highest of all hillocks is brought into contact with the lower surface of the second insulating interlayer is provided.

Semiconductor device and method of manufacturing the same

A semiconductor device, includes a semiconductor substrate, a first wiring layer formed on the semiconductor substrate, the first wiring layer containing a first via having a first aspect ratio and a first wire having a second aspect ratio, the first aspect ratio being equal to or larger than the second aspect ratio, and a second wiring layer overlying the first wiring layer, the second wiring layer containing a second via having a third aspect ratio and a second wire having a fourth aspect ratio, the third aspect ratio being smaller than the fourth aspect ratio.

Semiconductor device having dual damascene structure

A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.

Method of manufacturing semiconductor device

An electrical fuse comprises: an interconnect to be cut; and a first terminal and a second terminal which are respectively provided at both ends of the interconnect to be cut. The interconnect to be cut comprises: a first orientation film which contains copper as a main component and is oriented in a (111) plane; and a second orientation film which contains copper as a main component and is oriented in a (511) plane. The second orientation film is provided inside the first orientation film over a width direction of the first orientation film, which is perpendicular to a direction from the first terminal toward the second terminal, so as to partition the first orientation film. Accordingly, it becomes possible to securely cut the electrical fuse whose constituent material is copper, and moreover, to maintain a satisfactory cut state of the electrical fuse after the cutting.

Electrical fuse and semiconductor device

Growing community of inventors

Kanagawa, Japan

Toshiyuki Takewaki