Shindengen Electric Manufacturing Company Limited

Ricoh Company, Ltd.

Toshiyuki Takemori

Yuji Watanabe

Masato Itoi

Fuminori Sasaoka

Mizue Kitada

Shinji Kunori

Kazushige Matsuyama

Masato Kishi

Kimihiko Yamashita

Kikuo Saka

Kunihito Ohshima

Takeo Anazawa

Toshitaka Akimoto

Kunihito Oshima

Provided is a semiconductor apparatus includes: a gate electrode disposed inside a trench and opposedly facing a p type base region with a gate insulating film interposed therebetween on a portion of a side wall; a shield electrode disposed inside the trench and positioned between the gate electrode and a bottom of the trench; an electric insulating region disposed inside the trench, the electric insulating region expanding between the gate electrode and the shield electrode, and further expanding along the side wall and the bottom of the trench so as to separate the shield electrode from the side wall and the bottom; a source electrode electrically connected to an ntype source region and the shield electrode, wherein the shield electrode has a high resistance region positioned on an ndrain region side, and a low resistance region positioned on a gate electrode side.

Semiconductor device

A semiconductor apparatus includes: a gate electrode in a trench and facing a p type base region with a gate insulating film interposed therebetween on a portion of a side wall; a shield electrode in the trench and between the gate electrode and a bottom of the trench; an electric insulating region in the trench, the electric insulating region extending between the gate electrode and the shield electrode, and further extending along the side wall and the bottom of the trench to separate the shield electrode from the side wall and the bottom; a source electrode electrically connected to an ntype source region and the shield electrode. The shield electrode has high resistance regions at positions where the high resistance regions face the side walls of the trench, and a low resistance region at a position where the low resistance region is sandwiched between the high resistance regions.

A trench gate power MOSFET () includes: an n-type epitaxial layer (); a p-type body region () formed in the vicinity of an upper surface of the n-type epitaxial layer (); a plurality of trenches () formed so as to reach the n-type epitaxial layer () from an upper surface of the p-type body region (); and gates () formed in the trenches (). In some regions facing the p-type body region () in the n-type epitaxial layer (), p-type carrier extracting regions () are formed. According to the trench gate power MOSFET (), holes generated in a cell region can be effectively collected through the p-type carrier extracting regions () so as to further increase a speed of the switching operation.

Trench gate power semiconductor device

A disclosed semiconductor device provided with a power MOSFET includes: a semiconductor substrate constituting a drain; a trench formed on a surface of the semiconductor substrate; a gate electrode in the trench; a body diffusion layer on a surface side of the semiconductor substrate, the body diffusion layer being positioned adjacently to the trench and formed shallower than the trench; a source diffusion layer on the surface of the semiconductor substrate; a first interlayer insulating film formed on the gate electrode; and a source electrode film made of a metallic material and formed on the semiconductor substrate. A top surface of the gate electrode and a top surface of the first interlayer insulating film are formed in a recessed manner in the trench relative to the surface of the semiconductor substrate, and a surface portion of the semiconductor substrate for the trench is formed into a tapered shape.

Semiconductor device and manufacturing method thereof

MOS FETs are formed by a drain layer, a drift layer, P-type body areas, N-type source areas, gate electrodes, a source electrode film, and a drain electrode film. In parallel to the MOS FETs, the drain layer, the drift layer, the P-type diffusion area, and the source electrode filmform a diode. The source electrode filmand the P-type diffusion areaform an Ohmic contact. The total amount of impurities, which function as P-type impurities in each P-type body area, is larger than the total amount of impurities, which function as P-type impurities in the P-type diffusion area

Semiconductor device for reducing forward voltage by using OHMIC contact

The capacitance between the gate electrode film and the drain layer of semiconductor device is reduced while keeping the resistance low, with the breakdown voltage of the gate insulating film also being maintained at a sufficient level. A trenchis formed with the bottom of the trench at a comparatively shallow position in an N-epitaxial layerThe thickness of a bottom surface partof a gate electrode filmis formed so as to be thicker than other parts of the gate electrode filmAlso, when a P type body layeris formed, an interface between the P type body layerand an N-epitaxial layeris located at a deeper position than a bottom end of the gate electrode film

Semiconductor device having shallow trenches and method for manufacturing the same

In a semiconductor device in which gate trenches and source trenches are formed, when the semiconductor device is flatly viewed, Ntype source areas are formed in parallel with the gate trenches to ease the miniaturization of the semiconductor device. Ptype diffusion areas are separately formed in a direction orthogonal to the Ntype source areas and the gate trenches. Thus, the Ntype source areas and a P type body layer are formed in a laminated state, but the Ptype diffusion areas are not laminated. Therefore, the structure of a mesa section is extremely simple. Furthermore, gate electrode films are connected to one another by a connection member. Thus, the semiconductor device has such a structure as to easily secure electric connection to each gate electrode film from outside. According to the foregoing structure, it is possible to extremely ease the miniaturization of the semiconductor device.

An example semiconductor device is capable of preventing a buried diffusion region formed near the bottom surface of a source trench from diffusing to the extent that it contacts a gate trench in the vicinity of that buried diffusion region even if the accuracy of the photographic step of trench formation is not so high. A side wall is formed on the circumferential side of the source trench and then impurities are injected to the bottom surface of the source trench. When the impurities are heated and diffused, the buried P-type diffusion region is formed with a width almost identical to the width of the opening of the source trench or smaller than the width of the opening of the source trench. Thus, even when irregularities are generated in the manufacturing step and the buried diffusion region becomes larger than is necessary, it is possible to prevent contact of the buried diffusion region with the gate trench.

A technique is provided which makes it possible to reduce the area of a power MOSFET. A power MOSFETaccording to the invention is a trench type in which a source regionis exposed on both of a substrate top surfaceand an inner circumferential surfaceof a trench. Since this makes it possible to provide contact between the source regionand a source electrode filmnot only on the substrate top surfacebut also on the inner circumferential surfaceof the trench, source contact is provided with a sufficiently low resistance only on the substrate top surface, and the area of the device can be made smaller than that in the related art in which the source regionhas been formed in a larger area.

Method of manufacturing transistor

The capacitance between the gate electrode film and the drain layer of semiconductor device is reduced while keeping the resistance low, with the withstand voltage of the gate insulating film also being maintained at a sufficient level. A trench is formed with the bottom of the trench at a comparatively shallow position in an N-epitaxial layer . The thickness of a bottom surface part of a gate electrode film is formed so as to be thicker than other parts of the gate electrode film . Also, when a P type body layer is formed, an interface between the P type body layer and an N-epitaxial layer is located at a deeper position than a bottom end of the gate electrode film

A technique is provided which makes it possible to reduce the area of a power MOSFET. A power MOSFET according to the invention is a trench type in which a source region is exposed on both of a substrate top surface and an inner circumferential surface of a trench . Since this makes it possible to provide contact between the source region and a source electrode film not only on the substrate top surface but also on the inner circumferential surface of the trench , source contact is provided with a sufficiently low resistance only on the substrate top surface, and the area of the device can be made smaller than that in the related art in which the source region has been formed in a larger area.

Transistor and method of manufacturing the same

A technique for reducing an on-resistance of a transistor is provided. A power MOSFET of the present invention has a semiconductor material which is disposed under a polysilicon gate and composed of polysilicon into which impurities are doped at low concentration. Therefore, a depletion layer is expanded to the inside of the semiconductor material under the polysilicon gate. Since the electric field strengths are uniform from the surface of a drain layer to a depth of the bottom surface of the semiconductor material and a high electric field is not generated at one site, the avalanche breakdown voltage of the transistor is increased. Therefore, the concentration of impurities in drain layer can be made higher than that in a conventional transistor and thereby the on-resistance of the transistor 1 can be reduced.

Method of manufacturing a transistor

A technique for reducing an on-resistance of a transistor is provided. A power MOSFET of the present invention has a semiconductor material which is disposed under a polysilicon gate and composed of polysilicon into which impurities are doped at low concentration. Therefore, a depletion layer is expanded to the inside of the semiconductor material under the polysilicon gate. Since the electric field strengths are uniform from the surface of a drain layer to a depth of the bottom surface of the semiconductor material and a high electric field is not generated at one site, the avalanche breakdown voltage of the transistor is increased. Therefore, the concentration of impurities in drain layer can be made higher than that in a conventional transistor and thereby the on-resistance of the transistor can be reduced.

Growing community of inventors

Saitama, Japan

Toshiyuki Takemori