Sanyo Electric Co., Ltd.

Tokyo Sanyo Electric Co.

Toshiyuki Ozawa

Kazuhiro Kimura

Shigeaki Hayashibe

Takahiko Masumoto

Yutaka Hirakoso

Shizuka Ishimura

Munehiro Suka

Tatsuo Hiramatsu

Yoshikazu Tomida

Tetsuya Tokunaga

Shuji Motegi

Norio Yamashita

Akira Yamazaki

Takayuki Ohashi

Hiroyoshi Kaneyama

For frequency change, the VCO is controlled through a sub-charge pump circuit to make a determination as to whether or not a difference of dividing data between before and after the change is within a predetermined range. When it is determined that the difference is outside the predetermined range, the loop filer is forcibly charged in a charge time which is determined proportional to the difference in the dividing data, to thereby control an oscillation frequency of the VOC. A large VOC oscillation frequency change can be swiftly realized. Also, while the frequency change circuit is controlling the oscillation frequency, a time constant of the loop filter in the PLL circuit is preferably set at a small value, so that frequency change by the frequency change circuit can be swiftly achieved.

PLL synthesizer circuit

Superimposed FM data is demodulated to digital data. A synchronism reproducing circuit (data block detecting section) detects the front of blocks in the digital data to generate a block head signal (a station change timing signal), which is supplied to a control section of a station selecting microcomputer. When a station selecting key requests a change of the received station, station data corresponding to a requested station is supplied to the control section (a station selecting control section). When the block head signal is inputted after requesting the change of the station, the control section begins to output station change data to a PLL frequency synthesizer in order to change the frequency signal in a front end. This prevents a latter part of a block in received superimposed FM data from being NG data.

FM radio receiver and signal processing device used therein

A master (1) and a slave (3) are connected via a transmission line (5) for sending a clock CL; another transmission line (6) for bidirectionally sending data DT; and still another transmission line (7) for sending a control signal CE. Having turned a control signal CE into 'L,' the master (1) transmits an address code as data DT to the slave (3). Referring to the content of the transmitted address code, the slave (3) detects whether it is a data transmission from the master (1) to the slave (3) or vice versa. While a control signal CE remains 'H,' data transmission takes place. Data output from the slave (3) to the data line (6) is managed by a bus driver (22). The bus driver (22) is turned off during a period from when the clock CL became 'H' to when a control signal CE becomes 'L' after data transmission so that data transmission from the master (1) will not be adversely affected.

System for prioritizing slave input register to receive data

A scrambling key is generated from demodulated and error-corrected FM demodulation data for use in descrambling. During this process, if error correction has not been normally conducted to an object data packet, a subsequent descrambling operation is not executed to that data packet. In addition, a descrambling operation is not carried out if the object data packet is a parity packet.

Data processing device for FM multi-channel broadcasting

In a packet analyzing circuit, first and second key data are detected and stored in respective first and second key data registers. First and second key generation circuits generate first and second keys from the first and second key data. An exclusive OR operation is carried out to both keys so as to generate a scrambling key. Using the scrambling key as an initial value, a random number generator generates a PN code used for scrambling, so that scrambled data is descrambled by adding the PN code to the data. The first key generation circuit, which receives a control signal CON from a timing generation circuit, is controlled by the control signal CON such that a scrambling key is generated only when the random number generator needs an initial value.

Descrambling device

In accordance with the operation of an operating section 14, a control section 12 performs a reception control operation and demodulates a signal passing through a band pass filter 7 for extracting a multiplex signal using a multiplex signal demodulating section 8 when receiving a broadcast signal. A block synchronization circuit 16 of a synchronization circuit 9 carries out block synchronization processing on the demodulated signal. When block synchronization is established, a synchronization determination signal is supplied to a detecting section DET and the detecting section DET determines that a broadcasting station whose radio waves are currently being received is a multiplex broadcasting station.

FM multiplex broadcast receiving circuit for detecting presence or

In a decoding processing circuit of a digital signal receiver, a first comparison circuit detects that a prefix of packet data is inputted in a shift register on the basis of a count value of a counter circuit. In response to the result of detection, a pseudo-random binary sequence generation circuit outputs a pseudo-random binary sequence on the basis of a data group number and a data packet number outputted from the shift register and key data previously extracted by a key data fetch circuit. When a second comparison circuit detects that block data in the data packet is inputted in the shift register, an exclusive OR circuit exclusively ORs the pseudo-random binary sequence with receive data, so that decoded data is inputted in the shift register.

Digital signal receiver capable of receiving data encrypted and

In multiplex FM broadcasting, a digital signal is composed of a frame which consists of a predetermined number of blocks in the vertical direction, a block consisting of a predetermined number of bits in the horizontal direction and having a horizontal parity (error correcting code) for correcting errors in the horizontal direction and a vertical parity for correcting errors in the vertical direction. The block also has a control bit for determining whether the error correction in the horizontal direction is to be carried out only once. A decoding identification detector (20) detects the content of the control bit, a controller (12) controls the re-writing of the digital signal into a frame buffer (13) after the error correction of the digital signal in the vertical direction by an error corrector (14). The controller (12) also controls the provision of the digital signal stored in the buffer (13) to the error corrector (14) according to the content of the control bit, determining whether the second error correction in the horizontal direction is to be carried out.

Digital signal processing for controlling error correction based on the

An SI judging circuit in a service detecting section detects a service identification code included in a block included in received superimposed FM data. When the block represents an unnecessary service, the SI judging circuit generates a predetermined service detecting signal, which is supplied to a station selecting microcomputer. A user operates a station selecting key to request the change of the broadcasting station. When the change is requested, and also the service detecting signal indicating that the service included in the received block is not needed is supplied to the station selecting microcomputer by the SI judging circuit, a control section of the station selecting microcomputer outputs station data corresponding to the requested station to a PLL synthesizer, and then the frequency signal (tuning frequency) is changed at a front end. This enables data received during a period for receiving blocks for unnecessary services to be NG, and can prevent data of blocks including necessary services from being NG.

A digital phase comparator, to be used in a phase locked loop, for example, comprises a first and second input signal terminals receiving a first and second input signals, respectively, the phases of which are to be compared, and a pair of first and second delay flip-flops. The first input signal terminal is connected to a clock terminal of the first delay flip-flop and a reset or set terminal of the second delay flip-flop. The second input terminal is connected to a set or reset terminal of the first delay flip-flop and a clock terminal of the second delay flip-flop. An inverted or non-inverted output terminal of the first delay flip-flop is connected to a data terminal of the second delay flip-flop. An inverted or non-inverted output terminal of the second delay flip-flop is connected to a data terminal of the first delay flip-flop. An output signal associated with the phase difference between the first and second input signals is obtained from the output terminals of the first and second delay flip-flops.

Digital phase comparing apparatus

A superheterodyne receiver comprising a high frequency amplifier, a local oscillator implemented by a frequency synthesizer including a phase locked loop, a mixer, an intermediate frequency amplifier, an up down counter for providing data concerning frequency division rate of a programmable counter in the phase locked loop, characterized in that the up down counter is structured such that the counter is responsive to a command signal from an upward scanning switch to make an upward counting operation and is responsive to a command signal from a downward scanning switch to make a downward counting operation and is further responsive to command signals simultaneously obtained from these two upward and downward scanning switches to make a consecutive upward or downward counting operation, whereby a receiving channel is consecutively selected in the upward or downward direction in a fast scanning manner. Preferably, a fast scanning operation responsive to simultaneous depression of the two upward and downward scanning switches is stopped responsive to a receiving signal such as an intermediate frequency signal or a detected signal obtained when a broadcasting channel is selected. Preferably, a digital channel display is provided such that the data representative of the channel being selected obtainable from a control is transferred in a bit serial signal format to the display, wherein the pulses having a pulse width wider than a predetermined value are utilized for the purpose of data processing, thereby to eliminate any adverse affect due to noise during the transmission of the data.

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Ota, Japan

Toshiyuki Ozawa