Sanyo Electric Co., Ltd.

Toshiyuki Ohkoda

Shigeaki Okawa

Satoru Kaneko

Takao Myono

Shinichi Saeki

Yoshiaki Ohbayashi

Mamoru Yasuda

Shuji Osawa

Toshimitsu Taniguchi

Shuichi Kikuchi

Seiji Otake

Yasuhiro Takeda

Tsuyoshi Takahashi

Satoru Shimada

Kazuhiro Yoshitake

Tadayoshi Takada

Osamu Ikeda

Mitsuaki Morigami

Keizi Mita

Kazutomo Goshima

Shigeaki Ohkawa

A semiconductor device includes a trench formed in a surface of a semiconductor substrate. A conductor is embedded in the trench. A conductive layer is arranged adjacent to the trench on the surface of the semiconductor substrate. Semiconductor elements, which include sources provided by one of the conductor and the conductive layer and drains provided by the other one of the conductor and the conductive layer, are formed in a semiconductor element formation region. A planar wiring layer is embedded in the semiconductor substrate under the entire semiconductor element formation region and connected to the conductor.

Semiconductor device

This invention miniaturizes a package of a semiconductor device and simplifies a manufacturing procedure to reduce a manufacturing cost. A semiconductor wafer formed of a plurality of semiconductor chips formed with MEMS devices and wiring thereof on front surface thereof and a cap arrayed wafer disposed with a plurality of sealing caps are attached to seal the MEMS devices in cavities between them. Then, a plurality of via-holes is provided penetrating through the semiconductor wafer to form embedded electrodes therein, and bump electrodes are formed thereon. After this procedure, this structure is cut along scribe lines to be divided into each of packages.

Semiconductor device and manufacturing method of the same

This invention offers a ROM in which a user can program his digital data. In a memory cell array of the ROM, in which a plurality of interlayer insulation layers and a plurality of metal layers (including a bit line which makes an uppermost layer) are alternately stacked over each memory transistor, an insulation layer is formed on a tungsten plug in a first contact hole provided in a first interlayer insulation layer. The ROM is programmed by writing digital data '1' or '0' in each of the memory transistors according to whether a dielectric breakdown of the insulation layer is caused by a predetermined programming voltage (high voltage) applied from the bit line.

Nonvolatile semiconductor memory device

The object of the present invention is to provide a semiconductor device, which is suitable for use to connect electric condenser microphones. A semiconductor device, comprises: a conductivity-type substrate; an epitaxial layer formed on top of the substrate; island regions separating the epitaxial layer; an input transistor formed on one of the island regions; an insulation layer covering the surface of the input transistor layer; an expansion electrode formed above the insulation layer so as to provide an electrical connection to an input terminal of the input transistor; and resistivity of the epitaxial layer formed below the expansion electrode being in a range of 1000&#x2dc;5,000 &#x3a9;&#xb7;cm.

A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and P-type well regions are formed in the second epitaxial silicon layer. P+-type buried layers abutting on bottoms of the P-type well regions and N+-type buried layers abutting on bottoms of the P+-type buried layers and electrically isolating the P-type well regions from the single crystalline silicon substrate are formed. An MOS transistor is formed in each of the P-type well regions and a drain layer of the MOS transistor and each of the P-type well regions are electrically connected.

Charge pump device

The invention is directed to reducing of the number of steps in a BiCMOS process. A first N-wellA and a second N-wellB are formed deeply on a surface of a P-type semiconductor substrate. A first P-wellA is formed in the first N-wellA, and an N-channel MOS transistor is formed in the first P-wellA. The second N-wellB is used as a collector of a vertical NPN bipolar transistor. A second P-wellB is formed in the second N-wellB. The second P-wellB is formed simultaneously with the first P-wellA. The second P-wellB is used as a base of the vertical NPN bipolar transistor. An N+ emitter layer and a P+ base electrode layer of the vertical NPN bipolar transistor are formed on a surface of the second P-wellB.

Semiconductor device having MOS transistors and bipolar transistors on a single semiconductor substrate

In a charge pump device, occurrence of a latch up can be prevented and current capacity can be increased. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, P-type well regions are formed in the N-type epitaxial silicon layer separated from each other, and P-type lower isolation layers and P-type upper isolation layers are formed between the P-type well regions. Then a charge transfer MOS transistor is formed in each of the P-type well regions. The P-type single crystalline silicon substrate is biased to a ground potential or a negative potential.

A latch up in a charge pump device is prevented as well as a withstand voltage of an MOS transistor used in the charge pump device is increased with this invention. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and P-type well regions are formed in the second epitaxial silicon layer separated from each other. A P-type isolation layer is formed between the P-type well regions. A P+-type buried layer is formed abutting on a bottom of each of the well regions, an N+-type buried layer is formed abutting on a bottom of the P+-type buried layer, and a transistor for charge transfer is formed in each of the P-type well regions.

A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and a P-type well region is formed in the second epitaxial silicon layer. A P+-type buried layer is formed abutting on a bottom of the P-type well region, and an MOS transistor is formed in the P-type well region. The MOS transistor has a first source layer N+S of high impurity concentration, a first drain layer N+D of high impurity concentration and a second source layer N&#x2212;S and/or a second drain layer N&#x2212;D of low impurity concentration, which is diffused deeper than the first source layer N+S of high impurity concentration and the first drain layer N+D of high impurity concentration.

High breakdown voltage CMOS device

A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, and a P-type well region is formed in the N-type epitaxial silicon layer. A P&plus;-type buried layer abutting on a bottom of the P-type well region and an N&plus;-type buried layer partially overlapping with the P&plus;-type buried layer and electrically isolating the P-type well region from the single crystalline silicon substrate are formed. And then, an MOS transistor is formed in the P-type well region.

Large current capacity semiconductor device

In the semiconductor integrated circuit device, a first P type buried layer formed as an anode region and an N type diffused region formed in a cathode region are spaced from each other in the direction of the depth. This makes it possible to provide a semiconductor integrated circuit device in which a large depletion layer forming region can be provided in an N type region at a PN junction formed by first and second epitaxial layers and when a reverse bias voltage is applied to a diode element and in which a withstand voltage can be maintained by a depletion layer thus formed to prevent breakdown of elements in the device attributable to a breakdown current.

Semiconductor integrated circuit device and manufacturing method thereof

First, a stationary electrode layer is formed over a semiconductor substrate and an integrated network is composed in a circuit element area around the stationary electrode layer by electrode wiring forming each circuit element. A spacer is arranged on a passivation film in plural places. A dummy island is formed in an area between the circuit element area and the stationary electrode layer area. Supply potential Vcc is applied to the dummy island and ground potential GND is applied to a P -type separated area.

The object of the present invention is to provide a semiconductor device, which is suitable for use to connect electric condenser microphones. A semiconductor device, comprises: a conductivity-type substrate; an epitaxial layer formed on top of the substrate; island regions separating the epitaxial layer; an input transistor formed on one of the island regions; an insulation layer covering the surface of the input transistor layer; an expansion electrode formed above the insulation layer so as to provide an electrical connection to an input terminal of the input transistor; and resistivity of the epitaxial layer formed below the expansion electrode being in a range of 1000&tilde;5,000 &OHgr;&middot;cm.

The present invention is a semiconductor device, which is able to provide a desired output voltage of an ECM without signal loss caused by parasitic capacitances. Such a semiconductor device comprises a semiconductor substrate; integrated network elements including an input transistor being integrated on the semiconductor substrate, the input transistor having an input terminal; a first bonding pad connected to the input terminal of the input transistor for testing properties of the input transistor; a second bonding pad connected to one of the integrated network elements for external connection; and a surface area of the first coding pad being smaller than that of the second bonding pad.

Semiconductor device with HIHG resistivity

A stationary electrode layer is formed on a semiconductor substrate and a vibrating diaphragm is disposed on spacers The vibrating diaphragm is placed so as to protrude from an end of the semiconductor substrate and terminal pads to are placed with being exposed from the vibrating diaphragm

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Gunma, Japan

Toshiyuki Ohkoda