Fujitsu Corporation

Fujitsu Microelectronics Limited

Toshiyuki Nishii

Kazuya Taniguchi

Hiromichi Mizuno

Masayuki Takeshige

Tetsuji Tsutsumi

Tsutomu Terazawa

A semiconductor device for easily changing an operating voltage of an I/O circuit. The I/O circuit includes a first I/O cell, which operates with a first high-potential power supply, and a second I/O cell, which operates with a second high-potential power supply. The I/O circuit includes a control circuit for selectively activating the first and second I/O cells according to a voltage selection signal. In the I/O circuit, a signal having a voltage according to an operating voltage of the selected I/O cell is generated.

Semiconductor device including voltage level conversion output circuit

There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls data transfer between a synchronous memory circuit and the asynchronous circuit, and a control method therefor, which are used in the buffer circuit and the control method therefor. A data buffer circuit that is interposed between an image processing system and a main system includes a one-port RAM, a control signal generating section, an subsequent cycle address generating section, and a first selector. The first selector selectively outputs the present cycle address to an address of the one-port RAM when an access to the one-port RAM is a write access, and selectively outputs the subsequent cycle address to the address of the one-port RAM when the access to the one-port RAM is a read access.

Data buffer circuit, interface circuit and control method therefor

A memory having a plurality of memory cells and a plurality of redundant memory cells accesses a redundant memory cell in lieu of a failed memory cell. The memory is tested for failed memory cells. Addresses of detected failed memory cells are stored in a first set of registers, and addresses of redundant memory cells are stored in a second, corresponding set of registers. An external address is compared with the address stored in the first set of registers and if there is a match, the corresponding redundant memory cell address stored in the second register set is used to access the memory, in lieu of the external memory address.

Growing community of inventors

Kasugai, Japan

Toshiyuki Nishii