Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Toshiyuki Naka

Wataru Saito

Syotaro Ono

Hiroaki Yamashita

Shunji Taniuchi

Kazutoshi Nakamura

Akira Yoshioka

Yasunobu Saito

Akio Nakagawa

Hidetoshi Fujimoto

Tetsuya Ohno

Toru Takayama

Miho Watanabe

Yuki Kamata

Yoshinobu Sano

Naoko Yanase

Takeshi Uchihara

Tasuku Ono

Norio Yasuhara

Takaaki Yasumoto

Tsuyoshi Oota

Shingo Masuko

Hiroko Nonaka

Asami Gorohmaru

Kazuhide Abe

Atsuko Iida

Takako Motai

Miki Yumoto

Masaru Furukawa

Yukako Murakami

Yasunari Yagi

According to an embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a fifth semiconductor region of the second conductivity type, a gate electrode, and a second electrode. The first semiconductor region is provided on the first electrode. The first semiconductor region includes first portions and first protruding portions. The first portions are arranged along a first direction and a second direction perpendicular to the first direction. The first protruding portions respectively protrude from the first portions. The second semiconductor regions are spaced from each other and provided in the first semiconductor region. The third semiconductor region is provided on the first semiconductor region and the second semiconductor regions.

Semiconductor device and electrical apparatus

A semiconductor device includes a first nitride semiconductor layer having a first region, a second nitride semiconductor layer that is on the first nitride semiconductor layer and contains carbon and silicon, a third nitride semiconductor layer that is on the second nitride semiconductor layer and has a second region, a fourth nitride semiconductor layer on the third nitride semiconductor layer, the fourth nitride semiconductor layer having a band gap that is wider than a band gap of the third nitride semiconductor layer, a source electrode that is on the fourth nitride semiconductor layer and is electrically connected to the first region, a drain electrode that is on the fourth nitride semiconductor layer and is electrically connected to the second region, and a gate electrode that is on the fourth nitride semiconductor layer and is between the source electrode and the drain electrode.

Semiconductor device

According to one embodiment, a semiconductor device includes: a first switching element comprising a heterojunction comprising a first compound semiconductor layer and a second compound semiconductor layer; and a driver which applies a voltage to a gate of the first switching element to control turn-on and turn-off of the first switching element. The driver temporarily increases a gate voltage of the first switching element at a timing when the first switching element is turned on, during a period while the first switching element is on.

Semiconductor device with driver for switching element

A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode.

A semiconductor device includes a GaN-based semiconductor layer, a source electrode on the GaN-based semiconductor layer, a drain electrode on the GaN-based semiconductor layer, and a gate electrode formed on the GaN-based semiconductor layer between the source electrode and the drain electrode. A first layer is in contact with the GaN-based semiconductor layer between the gate electrode and the drain electrode.

A semiconductor device comprising: a Metal Oxide Semiconductor Field Effect Transistor including: a semiconductor substrate including a first semiconductor layer of a first conductivity type; second semiconductor layers of a second conductivity type extending in a depth direction from one surface of the semiconductor substrate, and having space each other; a first diode including a fifth semiconductor layer of the second conductivity type contacting the second semiconductor layer in one surface side of the semiconductor substrate, the first semiconductor layer and the second semiconductor layers; and an anode of the second diode connected to an anode of the first diode.

According to an embodiment, a semiconductor device includes a conductive substrate, a Schottky barrier diode, and a field-effect transistor. The Schottky barrier diode is mounted on the conductive substrate and includes an anode electrode and a cathode electrode. The anode electrode is electrically connected to the conductive substrate. The field-effect transistor is mounted on the conductive substrate and includes a source electrode, a drain electrode, and a gate electrode. The source electrode of the field-effect transistor is electrically connected to the cathode electrode of the Schottky barrier diode. The gate electrode of the field-effect transistor is electrically connected to the anode electrode of the Schottky barrier diode.

A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers.

Electric power semiconductor device and manufacturing method of the same

In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type or an intrinsic type. The device further includes a second semiconductor layer of the first conductivity type or the intrinsic type disposed above the first semiconductor layer. The device further includes a third semiconductor layer of a second conductivity type including a first upper portion in contact with the first semiconductor layer, a second upper portion located at a lower position than the first upper portion, a first side portion located between the first upper portion and the second upper portion, and a second side portion located at a lower position than the first side portion.

HEMT semiconductor device

A semiconductor device includes a semiconductor substrate and a plurality of gate electrodes including a part extended in a first direction in a plane parallel with the semiconductor substrate. The semiconductor substrate has a second semiconductor layer including a plurality of first conductive type pillars and second conductive type second pillars that are disposed on the first semiconductor layer, extending in the first direction in the plane parallel with the semiconductor substrate and in a third direction intersecting with a second direction orthogonal to the first direction, and arranged adjacent to each other in an alternate manner.

Semiconductor device that can maintain high voltage while lowering on-state resistance

According to one embodiment, a semiconductor device includes a substrate, a first semiconductor region, a second semiconductor region, a first electrode, a first electrode and a conducting section. The substrate includes a conductive region and has a first surface. The first semiconductor region is provided on the first surface side of the substrate and includes AlGaN (0&#x2266;X&#x2266;1). The second semiconductor region is provided on a side opposite to the substrate of the first semiconductor region and includes AlGaN (0&#x2266;Y&#x2266;1, X&#x2266;Y). The first electrode is provided on a side opposite to the first semiconductor region of the second semiconductor region and ohmically connects to the second semiconductor region. The conducting section electrically connects between the first electrode and the conductive region.

According to an embodiment, a semiconductor device includes a second semiconductor layer provided on a first semiconductor layer and including first pillars and second pillars. A first control electrode is provided in a trench of the second semiconductor layer and a second control electrode is provided on the second semiconductor layer and connected to the first control electrode. A first semiconductor region is provided on a surface of the second semiconductor layer except for a portion under the second control electrode. A second semiconductor region is provided on a surface of the first semiconductor region, the second semiconductor region being apart from the portion under the second control electrode and a third semiconductor region is provided on the first semiconductor region. A first major electrode is connected electrically to the first semiconductor layer and a second major electrode is connected electrically to the second and the third semiconductor region.

Growing community of inventors

Kanagawa-ken, Japan

Toshiyuki Naka