Texas Instruments Corporation

Toshiyuki Nagata

Hiroyuki Yoshida

Takayuki Niuya

Yoichi Miyai

Yoshihiro Ogata

Katsushi Boku

Masayuki Moroi

Atsushi Satoh

Michio Nishimura

Yasuhiro Okumoto

Kazuya Mori

Shuzoh Shiosaki

A method of forming a memory device (e.g., a DRAM) including array and peripheral circuitry. A plurality of undoped polysilicon gatesare formed. These gatesare classed into three groups; namely, first conductivity type peripheral gates, second conductivity type peripheral gates, and array gates. The array gatesand the first conductivity type peripheral gatesare masked such that the second conductivity type peripheral gatesremain unmasked. A plurality of second conductivity type peripheral transistors can then be formed by doping each of the second conductivity type peripheral gates, while simultaneously doping a first and a second source/drain regionadjacent each of the second conductivity type peripheral gates. The second conductivity type peripheral gatesare then masked such that the first conductivity type peripheral gatesremain unmasked. A plurality of first conductivity type peripheral transistors are formed by doping each of the first conductivity type peripheral gates, while simultaneously doping a first and a second source/drain regionadjacent each of the first conductivity type peripheral gates

Memory device with surface-channel peripheral transistors

In a DRAM array using a capacitor-under-bitline (CUB) layout, the plate layer of the capacitor is significantly reduced in area to reduce misalignments in connections between the bitline and the underlying transistors.

Reduced size plate layer improves misalignments for CUB DRAM

An open can-type stacked capacitor is fabricated by forming a conductive layer ( ) outwardly of a substantially uneven surface ( ). A step ( ) is formed in an outer surface ( ) of the conductive layer ( ). A base ( ) of a first electrode ( ) is formed by removing a predetermined thickness ( ) of at least part of the conductive layer ( ). The base ( ) is made of a portion of the conductive layer ( ) underlying the step ( ) by the predetermined thickness ( ). A sidewall ( ) of the first electrode ( ) is formed. A dielectric layer ( ) is formed outwardly of the first electrode ( ). A second electrode ( ) of the capacitor is formed outwardly of the dielectric layer ( ).

Method for fabricating an open can-type stacked capacitor on an uneven surface

A method of forming a memory device (e.g., a DRAM) including array and peripheral circuitry. A plurality of undoped polysilicon gates are formed. These gates are classed into three groups; namely, first conductivity type peripheral gates second conductivity type peripheral gates and array gates The array gates and the first conductivity type peripheral gates are masked such that the second conductivity type peripheral gates remain unmasked. A plurality of second conductivity type peripheral transistors can then be formed by doping each of the second conductivity type peripheral gates while simultaneously doping a first and a second source/drain region adjacent each of the second conductivity type peripheral gates The second conductivity type peripheral gates are then masked such that the first conductivity type peripheral gates remain unmasked. A plurality of first conductivity type peripheral transistors are formed by doping each of the first conductivity type peripheral gates while simultaneously doping a first and a second source/drain region adjacent each of the first conductivity type peripheral gates

Memory device with surface-channel peripheral transistor

A way to combine the metal bitline with the vertical interconnection to the capacitor over the bitline. In this class of embodiments, the vertical interconnect pillar is formed before fabrication of the bitline is completed. To accomplish this, the bitline metal is patterned using a step which allows it to extend vertically along the walls of the vertical interconnect pillar, but does not create any electrical connection between the bitline metal and the vertical interconnect pillar.

Structures and method with bitline self-aligned to vertical connection

A memory cell array ( ) is disclosed having variable pitch word lines and bit lines. The word lines include central word lines ( ) having a first pitch, and peripheral word lines ( ), situated proximate to the edge of the array ( ), having a second pitch that is greater than the first pitch. In a similar fashion, the bit lines include central bit lines ( ) having a third pitch, and peripheral bit lines ( ), situated proximate to the edge of the array ( ), having a fourth pitch that is greater than the third pitch. The increase in word line and bit line pitch can reduce the adverse results of proximity effects caused by the junction of the dense array features with the relatively open features of the adjacent periphery circuits.

Semiconductor memory device having variable pitch array

An open can-type stacked capacitor is fabricated by forming a conductive layer (,) outwardly of a substantially uneven surface (,). A step (,) is formed in an outer surface (,) of the conductive layer (,). A base (,) of a first electrode (,) is formed by removing a predetermined thickness (,) of at least part of the conductive layer (,). The base (,) is made of a portion of the conductive layer (,) underlying the step (,) by the predetermined thickness (,). A sidewall (,) of the first electrode (,) is formed. A dielectric layer (,) is formed outwardly of the first electrode (,). A second electrode (,) of the capacitor is formed outwardly of the dielectric layer (,).

A memory cell structure (10) includes a plurality of bit lines (12) and intersecting word lines (14). Bit line contacts (16) are spaced evenly apart on an associated bit line (12). A plurality of storage nodes (20) and associated storage node contacts (18) are provided. Storage nodes (20) and storage node contacts (2) are spaced evenly apart along the associated bit line (12). The storage nodes (20) and storage node contacts (18) are offset with respect to storage nodes (20) and storage node contacts (18) placed along adjacent bit lines (12).

Relaxed layout for storage nodes for dynamic random access memories

A ferroelectric random access memory (FeRAM) is disclosed. The FeRAM (400) provides a folded bit line array having memory cells (402a-402f and 404a-404d) with an area equivalent to 6F.sup.2, where F is a minimum feature size. Reduced array size is achieved by utilizing access transistors of complementary conductivity type within the array. First type memory cells (402a-402f) having n-channel access transistors (N400a-N400f), are formed next to second type memory cells (404a-404d) having p-channel access transistors (P400a-P400d). Bit lines (410a-410e) are arranged into bit line pairs, with a first bit line of each pair being coupled to first type memory cells (402a-402f) and the second bit line of each bit line pair being coupled to second type memory cells (404a-404d). When a word line is driven to a first voltage, ferroelectric capacitor data is driven on the first bit line, while the second bit line provides a reference voltage. When a word line is driven to a second voltage, ferroelectric capacitor data is driven on the second bit line and the first bit line provides a reference voltage.

Ferroelectric memory device having compact memory cell array

A dynamic RAM in which a groove (20) is formed on the main surface of a semiconductor substrate; a highly concentrated semiconductor layer (80) having one conductive type is formed inside the groove (20) to a depth sufficient to contain the first and second impurity diffusion areas (53) and (22), which are formed on the top of this groove and have the opposite conductive type; a capacitor C.sub.1 formed inside the groove (20), while a transfer gate Tr.sub.1 is formed on the highly concentrated semiconductor layer (80); and the diffusion area (53) is used to connect them.

Trench-type semiconductor memory device

A type of semiconductor device with a configuration characterized by the fact that an electroconductive film (90) is formed beforehand in connection to step (54a) of insulating film(54), and an electroconductive layer (63) with step from the aforementioned electroconductive film is coated to form the side contact of the memory cell. Even in the case when breakage takes place in electroconductive layer (63), the electrical conduction is still maintained via electroconductive film (90), and no wire breakage, in effect, takes place. In addition, it is possible to form the pattern for the aforementioned electroconductive layer by, for instance, etching back method without applying a special mask; hence, the manufacturing process is simplified.

Method of forming a trench-type semiconductor memory device

A type of semiconductor device with a configuration characterized by the fact that an electroconductive film (90) is formed beforehand in connection to step (54a) of insulating film (54), and an electroconductive layer (63) with step from the aforementioned electroconductive film is coated to form the side contact of the memory cell. Even in the case when breakage takes place in electroconductive layer (63), the electrical conduction is still maintained via substrate electroconductive film (90), and no wire breakage, in effect, takes place. In addition, it is possible to form the pattern for the aforementioned electroconductive layer by, for instance, etching back method without applying a special mask; hence, the manufacturing process is simplified.

French-type semiconductor memory device with enhanced trench

A semiconductor device in which a bit line (41), which is adhered to a contact hole (49) between polysilicon gate electrodes (35) and (36), is directly connected with an SiO.sub.2 film (53) having the same pattern on the gate electrodes; wherein an Si.sub.3 N.sub.4 layer (56) is buried outside the contact areas between the gate electrodes to approximately the same height as the SiO.sub.2 layer (53). The interlayer insulating film of the conventional memory cells array unit is no longer required, and it is not necessary to form contact holes in the interlayer insulating film. As a result, even if the gaps between the gates are designed to be small, there will be no short-circuiting between the bit line and word lines due to mask shifting, etc., making it possible to offer a highly integrated, highly reliable device.

Method of fabricating random access memory device having sidewall

A semiconductor device in which a trench-shaped groove (20) and a depression (100), which is formed by removing at least part of the area above and adjacent to the groove, are formed to be continuous on one side of the semiconductor substrate, in which aforementioned groove and aforementioned depression is buried a polysilicon conductive layer (103), the top of which conductive layer is converted into an insulator (102), the bottom of which insulating film (102) is contained in the depression (100).

Growing community of inventors

Plano, TX, United States of America

Toshiyuki Nagata