Sony Corporation

Toshiyuki Miyauchi

Takashi Yokokawa

Masayuki Hattori

Jun Murayama

Yasuhiro Iida

Tamotsu Ikeda

Hidetoshi Kawauchi

Kouhei Yamamoto

Takuya Okamoto

Makiko Kan

Hideyuki Suzuki

Naoki Yoshimochi

Kazukuni Takanohashi

Yuichi Mizutani

Yuji Shinohara

Atsushi Kikuchi

Hideyuki Matsumoto

Kazuo Watanabe

Satoru Hori

Kohei Yamamoto

Osamu Shinya

Kazuhiro Shimizu

Takashi Horiguti

Naomichi Kishimoto

Satoshi Okada

Makiko Yamamoto

Lachlan Bruce Michael

Yosuke Ueno

Hiizu Ootorii

Hiroyuki Kamata

Toshihisa Hyakudai

Takashi Hagiwara

Takanori Minamino

Haruo Togashi

Yuken Goto

Naoya Haneda

Kazunori Yasuda

Kazuhisa Funamoto

Koji Naniwada

Yoshifumi Miyajima

Tadaaki Yuba

Sachiya Tanaka

Provided is a sending control apparatus including a transmission path determination section that determines, from a plurality of transmission paths connected to different sending sections, respectively, one or more sending transmission paths that transmits one or a plurality of transmission object signals, respectively, obtained from sending data, on a basis of the number of sending transmission paths and prescribed information and a sending control section that controls the sending section connected to the sending transmission path so that the transmission object signal is sent via the sending transmission path.

Sending control apparatus, sending control method, signal synthesis apparatus, signal synthesis method, signal transmission system, and signal transmission method

A display panel includes a plurality of first unit pixels, each including: a data input terminal, a data output terminal, a display element, and a waveform shaping section. The display element is configured to perform display based on data inputted to the data input terminal. The first waveform shaping section is provided on a signal path from the data input terminal to the data output terminal.

Display panel having daisy-chain-connected pixels, pixel chip, and electronic apparatus

A display panel includes: a driver section configured to generate a first pixel packet including digital luminance data; a plurality of unit pixels successively connected, each of the unit pixels configured to perform a display operation, based on the digital luminance data of the first pixel packet, and one or more of the unit pixels configured to perform a detection operation of a physical quantity thereof to generate a second pixel packet including digital detection data acquired by the detection operation and then output the second pixel packet to a subsequent one of the unit pixels; and a receiver section configured to receive the second pixel packet.

Display panel, driving method, and electronic apparatus

A display panel includes: a display section including a plurality of unit pixels; and a display drive section configured to generate first pixel packets and supply the first pixel packets to the display section, the first pixel packets each including luminance data of a digital signal, the pieces of luminance data determining respective luminances of respective predetermined number of unit pixels of the plurality of unit pixels, and the first pixel packets being equal in number to the predetermined number of unit pixels.

Display panel, method of driving the same, and electronic apparatus

Disclosed herein is a decoding apparatus that performs soft-decision decoding on a linear block code, the apparatus including a hard-decision decoder configured to perform hard-decision decoding on a received word using a hard-decision decoding algorithm; and a soft-decision decoder configured to perform, using a soft-decision algorithm, soft-decision decoding merely on a received word for which the hard-decision decoder has failed in the hard-decision decoding.

Decoding apparatus and decoding method

The present invention relates to data processing apparatus and method, and a program which make it possible to scatter burst errors with respect to both codes of a product code. A block-wise interleaver performs interleaving A, which is a process of inputting data in the order of the column direction as one direction, and reading the data in the order of the direction diagonally downward to the right, NB bits by NB bits (=block by block) with respect to ND&#xd7;NB&#xd7;NA bits of a product code. Next, the block-wise interleaver performs interleaving B, which is a process of inputting data in the order of the column direction as one direction, and reading the data in the order of the row direction as the other direction, NB bits by NB bits with respect to (NC&#x2212;ND)&#xd7;NB&#xd7;NA bits representing the parity portion of an inner code indicated by P, of the product code. The present invention can be applied to, for example, a recording/reproducing apparatus.

Data processing apparatus and method, and program

The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P&#xd7;P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P&#xd7;P) 0-matrix. A check node calculatorsimultaneously performs p check node calculations. A variable node calculatorsimultaneously performs p variable node calculations.

Decoding apparatus, decoding method, and program to decode low density parity check codes

Disclosed herein is a receiving apparatus, including: a decoding section configured to receive and decode a low density parity check code; and a decoding control section configured to control a frequency of the decoding on the basis of conditional information that is an index indicative of a communication condition that influences power consumption in the decoding section.

Receiving apparatus, receiving method and program, and receiving system

A receiving apparatus receives a low density parity check ('LCPC') code and decode the LCPC code to provide for error check capabilities. A bit error rate ('BER') controlling section is the frequency of the LCPC by using an index comprised of BER conditional information that indicates communication conditions affecting the power consumption at the time of decoding. The frequency is controlled on the basis of a reception interval of the low density parity check code.

Disclosed herein is an information processor, including: a receiving section configured to receive an OFDM signal transmitted in accordance with an OFDM system; a FFT arithmetically operating section configured to carry out FFT for a signal within a predetermined interval of the OFDM signal; a delay profile estimating section configured to estimate delay profiles from the OFDM signal received by the receiving section; an inter-symbol interference amount estimating section configured to estimate inter-symbol interference amounts for a plurality of candidates for the predetermined interval, respectively, by using the delay profiles estimated by the delay profile estimating section; and a searching section configured to search for the candidate having the minimum inter-symbol interference amount estimated by the inter-symbol interference amount estimating section from among the plurality of candidates in the predetermined interval, and supply data on the candidate thus searched for as the predetermined interval to the FFT arithmetically operating section.

Information processor and information processing method, display device, and program

Disclosed herein is a receiving apparatus including: first to third position determination sections configured to determine the start position of an FFT interval which serves as a signal interval targeted for FFT by an FFT section; a selection section configured to select one of those start positions of the FFT interval which are determined by the first through the third position determination section; and the FFT section configured to perform FFT on the OFDM time domain signal by regarding the start position selected by the selection section as the start position of the FFT interval in order to generate the first OFDM frequency domain signal.

Receiving apparatus, receiving method, and program

The present invention can reduce power consumption at the time of tracing. The present invention provides a viterbi decoding apparatus for decoding convolution codes, which includes a path memory unit that stores one of two paths toward respective transition states of a convolution code, as a selected path, for a plurality of continuous time points, a tracing unit that traces a selected path stored in the path memory unit in a reversed-time direction, thereby decoding a convolution code at respective time points, each of the time points being prior to a predetermined trace-skipping period, and a control unit that controls the path memory unit, wherein the path memory unit has a storage area designed to store selected paths assuming respective transition states at respective time points, the storage area is divided into sub-areas from the lowest order of transition state, each of the sub-areas corresponding to predetermined number of bits, and reading data can be stopped for each sub-area, and the control unit designates sub-areas from which no selected path needs to be read at respective time points so as to stop reading data from the designated sub-areas.

Viterbi decoding apparatus

A decoding device that decodes demodulated data obtained by demodulating a quadrature modulated signal arising from digital modulation of a carrier and detects synchronization, the decoding device includes, a decoder configured to decode first demodulated data that is the demodulated data obtained by demodulating the quadrature modulated signal and is composed of in-phase axis data and quadrature axis data. The decoding device decodes second demodulated data obtained by interchanging the in-phase axis data and the quadrature axis data of the first demodulated data. A synchronization detector is configured to detect a boundary between predetermined information symbol sequences from first decoded data obtained by decoding the first demodulated data and detect the boundary from second decoded data obtained by decoding the second demodulated data. The synchronization detector selects and outputs one of the first decoded data and the second decoded data based on a result of the detection of the boundary.

Decoding device and method, receiving device and method, and program

A receiving device includes: a pilot extracting section; a first estimating section; a second estimating section; a third estimating section; a distortion correcting section; and a filter controlling section.

Receiving device, signal processing method, and program

A decoding device and method for decoding an LDPC code with high accuracy while suppressing an increase of the scale of a device. A check node calculator () performs check node calculations including calculations of a nonlinear function &#x3c6;(x) and its inverse function &#x3c6;(x) of the nonlinear function so as to decode an LDPC code. A variable node calculator () performs variable node calculation of a variable node so as to decode the LDPC code. The check node calculator () has an LUT which receives a fixed-point quantized value expressing a numerical value with a fixed quantization width and outputs the result of the calculation of the nonlinear function &#x3c6;(x) as a semi-floating point quantized value which is a bit sequence expressing a numerical value with a quantization width determined by a part of a bit sequence and an LUT which receives a semi-floating point quantized value and outputs the result of the calculation of the inverse function &#x3c6;(x) as a fixed point quantized value. The invention can be applied to e.g., a tuner for receiving a satellite broadcast.

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Kanagawa, Japan

Toshiyuki Miyauchi