Kabushiki Kaisha Toshiba

Toshiyuki Miyashita

Hiroaki Muraoka

Described herein is a dynamic latch circuit having a pair of control terminals connected to receive complementary first and second control clock pulses which are generated at a predetermined frequency, and a register section for detecting the voltage of an input signal, in response to each of the first and second control clock pulses, and generating an output signal from a capacitive output node which is charged or discharged in accordance with the voltage of the input signal and is subsequently set at a low potential or a high potential. The latch circuit further comprises a voltage-generating circuit for detecting, based on a period of time elapsed from the trailing edge of the last generated first control clock pulse, that the supply of the first control clock pulses has been stopped and fixedly setting the output node at the low potential.

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Yokohama, Japan

Toshiyuki Miyashita