Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Semiconductor Software Co., Ltd

Toshiyuki Matsubara

Shuzo Fujioka

Kenichi Takahira

Shigeru Furuta

Atsuo Yamaguchi

Takesi Inoue

Hiroki Takahashi

Hideo Matsui

It is intended to lower an increase of an area of an unused area or a wiring area, which is caused due to addition or enhancement of a particular function of a semiconductor device without significantly changing layout of the semiconductor device which has been previously designed. A semiconductor device ( A) has a layout in which a wiring area ( ) is surrounded by an extension block ( ) as a second semiconductor region and is completely sandwiched between a block ( ) and the extension block ( ). A plurality of wires ( ) are laid across the wiring area ( ) only at a single position between two adjacent ones of a plurality of pads ( ) in the wiring area ( ), to connect a CPU ( ) in the block ( ) and each of a ROM ( ), a RAM ( ) and an A/D converter ( ) in the extension block ( ) with each other.

Semiconductor device having a wire laid between pads

A voltage-controlled oscillator VCO capable of reliably generating an oscillation even if it, after stopping with electric charges remaining on both of its capacitors, is restarted under the same conditions. Even if the VCO is started with charges remaining on capacitors, N-channel transistors are both turned on because outputs of differential circuits are both at H level. N-channel transistors are both turned off because their gates are connected with the drains of the N-channel transistors. Therefore, in no case, the levels at points C and D as outputs on both sides of latch circuit go to L level at the same time.

Voltage-controlled oscillator and non-contact IC card including

A non-contact type IC-card with a simplified circuit arrangement which can select one of the PSK- and FSK-modulation methods at data transmission. A resonance frequency switching section is provided to halve the resonance frequency of a transmission and reception antenna. In the case of the PSK-modulation, the resonance frequency of the transmission and reception antenna is halved during one period of the original frequency at a modulation point so that the phase inverts for the phase modulation. In the case of the FSK-modulation, for the frequency modulation the frequency is switched over in accordance with the variation of the data. A PFSEL switch carries out the switching between both the modulation methods.

Non-contact IC card, non-contact IC card system, and non-contact IC card

In a non contact IC card for generating a power supply voltage from electric waves transmitted via wireless communication from a base unit, a reset signal generating circuit is provided to reset the internal circuits when the power supply voltage rises to a predetermined operating voltage and when it is lowered below a minimum voltage of voltages which ensure the normal operation of the internal circuits, thereby operations such as a writing operation in the internal circuits can be made stable and the time required for communication can be shortened.

Non contact IC card and a non contact IC card system

A microcomputer including an EEPROM in which data may be stored and from which stored data may be read either under control of a central processing unit of the microcomputer or under direct external control. The microcomputer includes separate inputs for data input and data output signals when storing and reading is under the control of the central processing unit and when storing and reading of data is under direct external control. The central processing unit may inhibit direct external control of storing data in and reading data from the EEPROM.

Microcomputer including internal and direct external control of EEPROM

A contact type IC card includes a power supply terminal, a reset terminal and an input/output terminal connected to an external device, an input/output circuit for receiving data from and delivering data to an external device through the input/output terminal, a data processing circuit connected to the input/output circuit for processing data, a memory circuit connected to the data processing circuit for storing data, and an internal reset signal generator for latching a predetermined potential when source power is applied from the external device through the power supply terminal, generating an internal reset signal by using the latched potential to bring the circuits info reset states, and stopping generation of the internal reset signal to release the circuits from reset states when a reset release signal is input from the external device through the reset terminal. A non-contact type IC card includes, as specific parts, a transmitting/receiving circuit, a battery and an oscillation unit for stopping oscillation of a clock signal and starting the oscillation of a clock signal to supply the clock signal to the data processing circuit when a trigger signal is received through the transmitting/receiving circuit. A reset sequence is performed reliably and consumption of the battery is suppressed.

Non-contact IC card

In an EEPROM, a column decoder control register stores, in accordance with a first signal on a system bus, a state indicating whether one byte of bit lines or all of the bit lines are selected. When the column decoder control register stores the state for selecting all of the bit lines, a column decoder selects a full Y-gate so that the same data is latched in a full column latch by latching data once. The latched data is written by a controller into all bytes in a page.

EEPROM, write control method for EEPROM, and IC card

A non-contact IC card include a data transmitting/receiving device, a memory, a CPU, a first determining device, a second determining device, and a stopping device. When the data transmitting/receiving device receives a request signal, the first determining device determines whether first system identification information stored in the memory agrees with second system identification information contained in the request signal. At the same time, the second determining device determines whether use of the IC card indicated by use authorization information stored in the memory is authorized. When the first and second system identification information do not agree or when the use authorization information indicates that use of the IC card is not authorized, the stopping device stops the operation of the CPU until the next request signal is received.

A non-contact integrated card includes a data transmitting and receiving circuit, a data processing unit connected with the data transmitting and receiving circuit, a clock generating circuit for generating a clock signal and for supplying the clock signal to the data processing unit, a battery for supplying electrical energy to the data transmitting and receiving circuit, the data processing unit and the clock generating circuit, and a clock stopping circuit for stopping the generation of the clock signal by the clock generating circuit upon receipt of a clock stop signal from outside of the card. The inclusion of the clock stopping circuit which stops the generation of the clock signal in response to a clock stop signal input from an external circuit makes it possible to suspend the consumption of energy produced by the battery after testing, during shipping, and before use of the card.

Non-contact integrated circuit card

In a non-contact IC card, when the card is in a standby mode of operation a CPU provides a command to inhibit the application of a clock signal to digital circuitry including the CPU and/or to inhibit the application of an operating voltage to analog circuitry, except for an antenna circuit and a trigger signal demodulating circuit, so that power consumption in the standby mode is reduced. For transfer of data between the IC card and an external device, a trigger signal derived by demodulating received data in the trigger signal demodulating circuit is used to apply the clock signal to said digital circuitry and the operating voltage to all of the analog circuitry.

A memory system storing data detects and corrects an error in the stored data. The memory device includes a coding circuit for generating a systematic code including a data word and an error checking and correcting (ECC) code when the data word is supplied from a data bus during data writing, a memory cell array for storing the systematic code, and a sense amplifier for reading the systematic code from the memory cell. An error checking and correcting system generates a syndrome from the systematic code, decodes the syndrome to determine whether an error exists, identifies a bit position at which an error has occurred, and corrects the error contained in the data word by inverting a bit of the data word in the position at which the error has occured. The system includes a multiplexer for outputting the corrected data word to the data bus and a code reading circuit, for example, an ECC code register, for reading the ECC code generated by the coding circuit directly into the data bus. With this arrangement, it is possible to immediately and independently check the function of the coding circuit without influence from the memory cell array.

Memory device

A microcomputer comprises EEPROM provided as a fixed storage unit and a CPU for controlling the operation of the EEPROM, in which the EEPROM contains a divider which divides a stable clock signal from the outside of the microcomputer and converts it to a clock signal with a desired frequency, the clock signal is used as a synchronizing signal necessary for the writing data into the EEPROM. The CPU controls the operation of the EEPROM and sets the dividing ratio of the divider contained in the EEPROM at a desired value in accordance with the assignment from the outside of the microcomputer.

Microcomputer

A microprocessor system including an EEPROM with a page mode writing function that prevents writing of erroneous data. The circuit includes a memory cell array divided into a plurality of pages each having a predetermined number of bytes, a data latch for latching bytes corresponding to a page, an exterior write control circuit which enables the data latch in response to a signal from the CPU to latch a sequence of bytes corresponding to a page, and an interior write control circuit which enables the memory cell array so that the bytes latched in the data latch are transferred therefrom to a page of the memory cell array. The exterior write control circuit includes a time measurement circuit and an interior write suppression circuit. The time measurement circuit measures the time which elapses from the initiation of the latching of bytes into the data latch, and outputs an overflow signal when the measured time exceeds a predetermined limit. The interior write suppression circuit suppresses the interior write control circuit, in response to the overflow signal, so that the transfer of erroneous data bytes from the data latch to a page of the memory cell array is prevented.

Microprocessor having miswriting preventing function

An IC card includes an addressable CPU having a memory space including a special area including a first plurality of memory addresses which are addressable with a short instruction word, first and second memories in which test and application programs are stored, respectively, a bus which connects the CPU and the first and second memories, a first selection circuit for forming a first memory mapping arrangement in which at least a portion of the first memory is superimposed on the special area, a second selection circuit for forming a second memory mapping arrangement in which at least a portion of the second memory is superimposed on the special area, a detection circuit for detecting the execution of the test program or the application program, and a changeover circuit arranged to selectively operate the first and second selection circuits according to the result of detection executed by the detection circuit. The above-described arrangement makes it possible to effectively use the special area to efficiently execute either the application program or the test program.

IC card

An IC card has a CPU, a first memory for storing a test program, a second memory for storing an application progam, a bus connecting the CPU and the first and second memories. A detection circuit for detecting whether the CPU has began executing the application program stored in the second memory, and a disconnection circuit for disconnecting the first memory from the bus when the detection circuit detects that the CPU has begun executing the application program. The above-described arrangement makes it impossible to access the test program in the system ROM from the application program thereby preventing the occurrence of incorrect access.

Growing community of inventors

Itami, Japan

Toshiyuki Matsubara