Citizen Watch Company, Ltd.

Toshiyuki Kishi

Takashi Toida

Yasuhiro Sakurai

In a semiconductor device comprising an N channel MOS device, and P channel MOS device, or additionally comprising a MONOS device, provided with a gate insulating film and gate electrode formed on a semiconductor substrate or semiconductor layers of a SOI substrate, respectively, the gate insulating film of at least the P channel MOS device is made up of a dual-layer film consisting of a gate oxide film composed of a silicon dioxide film, and a gate silicon nitride film.

Semiconductor device and fabricating the same

A MOS device comprises a p-channel semiconductor device and n-channel semiconductor device, which are formed on top of an SOI substrate consisting of a supporting substrate, an insulation film, and a semiconductor layer patterned in a plurality of islands. In the peripheral region of respective islands of the semiconductor layer, boundary films, thicker than respective gate oxide films, are formed, and a boundary film formed on the semiconductor layer for the n-channel semiconductor device is thinner than another boundary film formed on the semiconductor layer for the p-channel semiconductor device. A field doped layer,may be preferably provided in the peripheral region of the semiconductor layer of the n-channel semiconductor device,. In the MOS device fabricated as above, leakage current that occurs in a parasitic MOS region in an environment under exposure to radiation is reduced, ensuring stable operation.

MOS device and method of fabricating the same

A MONOS nonvatile memory transistor includes a semiconductor substrate, a memory insulator film on the semiconductor substrate composed of a tunnel insulator film, a memory nitride film and a top oxide film, and a memory gate electrode on the memory insulator film. The tunnel insulator film is constituted of a silicon nitrided oxide film containing oxygen and nitrogen and an oxygen-rich silicon nitrided oxide film or a silicon oxide film to make the nitrogen content of the tunnel insulator film in the vicinity of its interface with the semiconductor substrate greater than its nitrogen content in the vicinity of its interface with the memory nitride film. By this, the barrier height of the tunnel insulator film to holes in the semiconductor substrate is lowered without lowering the barrier height thereof to holes captured on the memory nitride film side.

Semiconductor nonvolatile memory transistor and method of fabricating

A semiconductor device is provided by forming an insulating film on a supporting substrate and a semiconductor layer on the insulating film, forming an MOS semiconductor component having a source, a drain and a gate on the semiconductor layer, forming at least one of the source region of the semiconductor layer provided with the source and the drain region thereof provided with the drain to have greater thickness than a channel region of the semiconductor layer provided with a gate oxide film and a gate on the gate oxide film, and forming at least one of the source and the drain to be separated from the insulating film by the semiconductor layer of opposite conductivity type therefrom. A bulk layer of the same conductivity type as the semiconductor layer is provided in a thick region of the semiconductor layer. An MNOS or MONOS semiconductor non-volatile memory cell can be formed by replacing the gate oxide film with a memory gate insulating film consisting of a silicon oxide film and a silicon nitride film.

Method of fabricating an SOI device having a channel with variable

SOI device having a channel with variable thickness

An MOS device including a p-channel semiconductor device and an n-channel semiconductor device, which are formed on top of an SOI substrate consisting of a supporting substrate, an insulation film, and a semiconductor layer patterned in a plurality of islands. In the peripheral region of respective islands of the semiconductor layer, boundary films, thicker than respective gate oxide films, are formed, and a boundary film formed on the semiconductor layer for the n-channel semiconductor device is thinner than another boundary film formed on the semiconductor layer for the p-channel semiconductor device. A field doped layer 11 may be preferably provided in the peripheral region of the semiconductor layer of the n-channel semiconductor device 41. In the MOS device fabricated as above, leakage current that occurs in a parasitic MOS region in an environment under exposure to radiation is reduced, ensuring stable operation.

Mos device and method of fabricating the same

A radiation dosimeter including a series circuit of an MONOS semiconductor and a resistor or an MOS or MONOS semiconductor device whose channel conductivity type is opposite from that of the first said MONOS semiconductor device. The MONOS semiconductor device is an electrically rewritable non-volatile memory cell having a gate insulating film consisting of a tunnel oxide film, a silicon nitride film and a top oxide film. The resistor is made of polycrystalline silicon which is little affected by exposure to radiation. The series circuit is connected between a source voltage and ground (GND) and a detection signal is obtained from the connection point between the members of the series circuits.

Radiation dosimeter

On a semiconductor substrate (1) is provided an insulator film, on which is formed a lower gate electrode including a first lower gate electrode (5a) and a second lower gate electrode (5b), on which lower gate electrode is formed a lower gate insulator film. On the lower gate insulator film is disposed a device region (9), on which is disposed an upper gate electrode (13) by way of an upper gate insulator film. The device region (9) has island-shaped patterns. The first lower gate electrode (5a) is placed in substantially the middle part of the device region (9), while the second lower gate electrode (5b) is provided in parallel with the first lower gate electrode (5a) and at a boundary between the device region (9) and the insulator film. The upper gate electrode (13) is positioned orthogonal to the lower gate electrodes (5a, 5b). This configuration will make it possible to inhibit the occurrence of current leakage due to parasitic transistors.

Growing community of inventors

Tokorozawa, Japan

Toshiyuki Kishi