Nec Corporation

Toshiyuki Kanoh

Kenji Igarashi

Akihiro Shiratori

Chizuru Matsumura

Data transfer mode between a plurality of circuit mod modules connected to a data bus is dynamically switched between a time division, space-division multiplexing and so forth for improving data transfer efficiency. For example, the data bus of 4n bit width is used as two data bus of 2n bit width in certain period (transfer mode &ldquo;b&rdquo;), as one data bus of 4n bit width in a certain period (transfer mode &ldquo;a&rdquo;), and further as four data bus of n bit width in a further certain period (transfer mode &ldquo;c&rdquo;). A command of switching of the transfer mode is performed by a transfer control circuit common to respective circuit modules. In response to command of the transfer mode, switching of the bit width of data and switching of the bus connecting condition are performed by the bus adapter circuit.

Data transfer control apparatus, data transfer control system and data transfer control method

A contents addressable memory circuit includes an inputting section, a contents addressable memory section and a control section. The inputting section divides an input data into n (n is an integer equal to or larger than 2) data blocks and supplies the n data blocks and an input address. The contents addressable memory section performs a data retrieving operation in units of data blocks to output addresses and coincidence flags corresponding to the data blocks. The coincidence flag is indicative of whether there is a data coincident with the corresponding data block. The control section outputs one of the outputted addresses based on the outputted addresses and the coincidence flags.

Contents addressable memory circuit for retrieval operation in units of

In a data processing device for use in a carrier transmission system in processing a device input signal of a plurality of channels, a single data processing circuit (21) and a multiport RAM (33) are used together with a write and read clock counter (51(1)) in place of a great number of data processing circuits, equal in number to an integral multiple of the number of channels, and a likewise great number of sequential circuits, such as D-type flip-flops. Through a supply arrangement which is preferably a selector (41) for selectively supplying a test signal to the RAM, a processed output signal is supplied from the data processing circuit to the RAM as a processed input signal for storage as memorized signals according to the channels and for read out as a device output signal. If desired, additional clock counters (51(2) to 51(N)) are used for read out of the memorized signals as additional device output signals. The stored test signal may be read out as a RAM test output signal, which can be processed by the data processing circuit, supplied through the selector, stored in the RAM, and read out as a processing circuit test output signal.

Data processing device comprising a multiport RAM as a sequential circuit

A matrix arithmetic circuit includes an address generator, a first multiplier, a second multiplier, and an accumulator. The address generator generates addresses of first, second, and third memories to read out matrix elements from the first, second, and third memories at predetermined timings. The first multiplier multiplies the first and second matrices. The second multiplier multiplies the multiplication result from the first multiplier and the third matrix. The accumulator accumulates the multiplication result from the second multiplier to obtain an arithmetic result.

Matrix arithmetic circuit

A CIF converter has N multipliers (where N is smaller than five) and N integrators connected respectively to the outputs of the N multipliers. Every five horizontal lines of an input NTSC or television signal is stored in memory. On a pixel-by-pixel basis first and second half segments of a luminance component of the stored lines and I and Q chrominance components of the stored lines are transferred from corresponding pixel positions of the memory to the N multipliers at a speed higher than the speed at which the input signal is stored into the memory, and weighted by tap weight coefficients having unique values corresponding respectively to the five horizontal lines. The weighted five-line pixel data of each of the video signal components are then summed by each integrator and stored back into the memory and sequentially read therefrom at a speed equal to the writing speed.

CIF converter with reduced multipliers

An arithmetic circuit for calculating and accumulating absolute values of differences between first and second numerical values having a predetermined bit length and represented by 2's compliment notation is provided by a first inverter for inverting the second numerical value to produce an inverted value; a first adder receiving the first numerical value and the inverted numerical value and generating a sum as a first addition result; and a selector receiving the first addition result from first adder and an inverted addition result from the first adder via a second inverter and outputting a selected value based on the sign of the first addition result. A correcting value generating circuit generates a correcting value based on the sign of the first addition result. A second adder receives the selected value, the correcting value and a delayed addition result and generates a sum as a second addition result, which is output to a first delay circuit. The first delay circuit delays the second addition result by a predetermined delay and outputs the delayed addition result as an operation result while providing the delayed addition result to the second adder. Additional delay circuits responsive to a clock signal can be operatively coupled between the selector and the second adder to match the speeds of the selector and the first delay circuit.

Arithmetic circuit for calculating and accumulating absolute values of

An absolute value calculating circuit for producing an absolute value of the difference between first and second numerical values. The circuit includes a first inverter for inverting the first numerical value, a first adder for adding the inverted first numerical value and the second numerical value, and a second inverter for inverting the output of the first adder. The circiuit further includes a second adder for adding 1 to the output of the adder and a selector for selecting and outputting, as the absolute value of the difference between the first and second numerical values, either the inverted output of the first adder or the output of the second adder in accordance with a sign of the output of the first adder.

Absolute value calculating circuit having a single adder

A circuit for comparing the magnitudes of two binary signals using five n-channel MOSFET transistors, one p-channel MOSFET transistor and two inverters. The circuit includes two input terminals, an auxiliary input terminal, an output terminal, and terminals for connecting the comparing circuit to a power supply and ground. When the binary signal applied to the first input terminal exceeds the binary signal applied to the second input terminal, the output is a first logic level. Conversely, when the binary signal applied to the second input terminal exceeds the binary signal applied to first input terminal, the output is a second logic level opposite to the first level. If the binary signals applied to the first and second input terminals are the same logic level, the output is the same logic level as the binary signal applied to the auxiliary input terminal. The circuit can be arranged in various configurations, including one in which a resistor is used in place of the p-channel MOSFET. A number one-bit comparing circuits can be cascaded together to form an n-bit comparing circuit.

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Tokyo, Japan

Toshiyuki Kanoh