Texas Instruments Corporation

Hitachi, Ltd.

Other

Toshiyuki Kaeriyama

Yoshitaka Tadaki

Toshihiro Sekiguchi

Keizo Kawakita

Songsu Cho

Michio Nishimura

Katsuo Yuhara

Michio Tanaka

Hideo Aoki

Jun Murata

Kazuhiko Saitoh

Shinya Nishio

Toshikazu Kumai

Yuji Ezaki

Minoru Ohtsuka

Kazuhiko Saito

Masayuki Yasuda

Takashi Hayakawa

Takeshi Sakai

Takafumi Tokunaga

Kiyomi Katsuyama

Hisao Asakura

Akihiko Konno

Takatoshi Kakizaki

Fumiaki Saitoh

Katsutoshi Matsunaga

Yoshimi Torii

Takeshi Harada

Youichiro Imamura

Hideo Nagasawa

Hironori Ishimoto

As for the method that modulates optical path length by the position of reflection plane of light, the movement of the position-movable plate in micrometer-size electromechanical device can be restricted by the stopping plates placed above and below the edge of the position-movable plate, the distance between the stopping plates may be set depending on the desired amount in modulating the optical path length. The voltage differential in the device is operable to create electrostatic attraction, to perform transition movement of the position-movable plate between the stopping plates, the light reflector connected to the position-movable plate takes at least two states in positioning, enabling to modulate the optical path length of reflected light by the light reflector with high reproducibility and high accuracy.

Micro-electromechanical device

A system and method for regulating micromirror position in a digital micromirror device. The system and method adjusts micromirror operating temperature and/or a reset sequence of the micromirror by determining a desired tilt angle, adjusting voltage potentials of signals in a reference reset sequence, and saving the adjusted reset sequence. The adjustments are used to alter a voltage potential difference between micromirrors of the digital micromirror device and respective address lines, thereby allowing for a precise regulation of a tilt angle of the micromirrors. Additionally, the operating temperature of the digital micromirror device may also be controlled to regulate micromirror position. The precise control of the tilt angle of the micromirrors permits the use of digital micromirror devices in systems requiring fine focus and increased focus depth, such as photolithography and holography.

System and method for regulating micromirror position

Device and method for a damping function to reduce undesirable mechanical transient responses to control signals. In one aspect of the present invention, the damping function may be used to reduce overshoot and oscillation when a digital micromirror is driven from a landing plate to the flat or neutral position. In another aspect of the present invention, the damping function may be used to reduce transient resonance of a digital micromirror when the micromirror is driven to a landing plate.

Damped control of a micromechanical device

A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.

Method of manufacturing semiconductor integrated circuit devices having a memory device with a reduced bit line stray capacity and such semiconductor integrated circuit devices

To suppress undesired scattered light and leaking light so as to improve the optical function and reliability. In this DMD, as the address circuit of one cell, SRAM is formed monolithically on the principal surface of silicon substrate , and, on said SRAM , reflective digital optical switch or optical modulating element is formed monolithically as one cell made of three layers of a metal, such as aluminum, via oxide film . Each reflective optical modulating element has bias bus and yoke address electrodes as the first metal layer, torsional hinge , hinge supporting portions , yoke , and mirror address electrodes as the second metal layer, and mirror as the third metal layer. Optical absorptive and nonconductive film is formed to cover a portion or all of the first metal layer and to cover underlying film (insulating film) . In addition, said film is formed to bury hole formed on the surface of the third metal layer.

Micro-electromechanical system

A method of fabricating a DRAM integrated circuit structure ( ) and the structure so formed, in which a common interconnect material ( ) is used as a first level interconnection layer in both an array portion ( ) and periphery portion ( ) is disclosed. The interconnect material ( ) consists essentially of titanium nitride, and is formed by direct reaction of titanium metal ( ) in a nitrogen ambient. Titanium silicide ( ) is formed at each contact location (CT, BLC) as a result of the direct react process. Storage capacitor plates ( ) and the capacitor dielectric ( ) are formed over the interconnect material ( ), due to the thermal stability of the material. Alternative processes of forming the interconnect material ( ) are disclosed, to improve step coverage.

Titanium nitride metal interconnection system and method of forming the same

A method of fabricating a DRAM integrated circuit structure (30) and the structure so formed, in which a common interconnect material (42, 48) is used as a first level interconnection layer in both an array portion (30a) and periphery portion (30p) is disclosed. The interconnect material (42, 48) consists essentially of titanium nitride, and is formed by direct reaction of titanium metal (40) in a nitrogen ambient. Titanium silicide (44) is formed at each contact location (CT, BLC) as a result of the direct react process. Storage capacitor plates (16, 18) and the capacitor dielectric (17) are formed over the interconnect material (42, 48), due to the thermal stability of the material. Alternative processes of forming the interconnect material (42, 48) are disclosed, to improve step coverage.

Titanium nitride metal interconnection system and method of forming the

A method of making semiconductor devices which enables control of the impurity concentration and fine patterning by making removal of residual stress due LOCOS oxidation compatible with the formation of deep wells. A selective oxide layer is formed for separating element regions on a principal plane of a semiconductor substrate, for example, a p.sup.- -type silicon substrate 1. A mask is formed (for example photoresist 47) on the surface including the selective oxide layer and impurities (for example phosphorous) of a conductivity type opposite that of the semiconductor substrate are introduced via an opening in the mask. Then the selective oxide film is annealed by a high-temperature treatment while a deep well (for example n-type deep well 50) is formed by introducing the impurities.

Method of manufacturing semiconductor device

A method for fabricating DRAMs each having a COB structure, and the semiconductor device formed by this method, are provided. In one embodiment, the word line and/or bit line is covered with an insulating film having a comparatively small etching rate. Contact holes are formed while being defined by those insulating films in self-alignment.

Method of manufacturing semiconductor device with increased focus margin

In an embodiment of a method of manufacturing semiconductor integrated circuit devices according to the present invention, word lines are provided in a straight form, which serve as gate electrodes of two selecting MOSFETs formed symmetrical about a center portion of an active region surrounded by a LOCOS oxide film on a semiconductor substrate, and bit lines have straight segments and protruding segments. Each protruding segment is formed to protrude from the bit line and is connected through a first contact hole to a first semiconductor region formed at the center portion of the active region. The straight line segments and the protruding segments are formed separately by two separate exposure steps.

Method of manufacturing semiconductor integrated circuit devices using

A semiconductor device, such as a dynamic RAM, and method of making it. A number of stacked cell capacitors are placed at a prescribed spacing in an alignment direction on top of a p.sup.- -type silicon substrate (1). Each capacitor has a nearly perpendicular cylindrical lower electrode (cylindrical polysilicon layer (96)), a dielectric film (silicon nitride film (77)), and upper electrode (plate electrode (78) made of polysilicon). The spacing in the alignment direction is smaller than the inner diameter of the lower electrode.

Method of forming a semiconductor device have a screen stacked cell

A phase shifting mask is used for manufacturing a semiconductor integrated circuit device including a conductor pattern in which the line width of patterned conductor strips or the space between patterned conductor strips is not constant. For main transparent areas in the mask corresponding to the conductor pattern, auxiliary pattern segments are provided for compensating changes in the phase distribution of transmitted light caused by changes of the line width or the space. Alternately, the spaces between the conductor strips are adjusted to suppress the changes in the phase distribution of transmitted light. Whether the auxiliary pattern segments should have the phase shifting function is determined depending upon the disposition of the main transparent areas.

Method of manufacturing a semiconductor integrated circuit device using

A process of cleaning debris (24) from a partially-sawn semiconductor wafer (10). The method of the present invention includes cleaning a partially fabricated wafer (12) that may have fabricated on it a micromechanical device (16) which can be easily damaged by particles (24) generated by the partial-saw process, such as oxide particles. The present invention includes cleaning the partially-sawn wafer with a solution including diluted hydrofluoric acid and an alkyl glycol. Clean-up using this solution accomplishes two goals. First, it removes debris including oxide particles on the wafer surface and in the kerfs (22), and second, reduces the depth of damage in the surface (26) of a CMOS layer (14) proximate the kerf (22) which has been determined to be a source of particles generated after a wafer cleanup process. A subsequent megasonic process is utilized to acoustically vibrate the wafer while bathed in deionized water to further remove any other particles. After the clean-up process of the present invention, the semiconductor wafer is completed by performing at least one more semiconductor process. An substantially improved yield is realized by utilizing the cleaning process of the present invention.

Method of cleaning wafer after partial saw

The etch-back amount of a silicon oxide film of a memory array which is a higher altitude portion is increased when etching back and flattening the silicon oxide film by arranging a first-layer wiring on a BPSG film covering an upper electrode of an information-storing capacitative element only in a peripheral circuit but not arranging it in the memory array. Thus, a DRAM having a stacked capacitor structure is obtained such that the level difference between the memory array and peripheral circuit is decreased, and the formation of wiring and connection holes are easy.

Growing community of inventors

Ibaraki-ken, Japan

Toshiyuki Kaeriyama