Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Matsushita Electronics Corporation

Toshiyuki Honda

Hiroshige Hirano

Hirokazu So

Masahiro Nakanishi

Masayuki Toyama

Shigekazu Kogita

Masato Suto

Keisuke Sakai

Takuji Maeda

Tatsuya Adachi

Yoshihisa Inagaki

Manabu Inoue

Tadashi Ono

Nobuyuki Moriwaki

Seiji Nakamura

Keizo Miyata

Tetsushi Kasahara

Isao Kato

George Nakane

Tetsuji Nakakuma

Hirofumi Nakagaki

Teruo Akashi

Shigeo Chaya

Kunihiro Maki

A memory controller includes: a memory that holds a physical block counter including the number of erase times, a logical block counter including the number of write times, and a logical-physical conversion table; and a control unit that writes data to any physical block address. When the control unit receives a writing data instruction, the control unit updates the number of write times corresponding to the write destination logical block address, if the number of write times corresponding to the write destination logical block address is large, the control unit allocates to the write destination logical block address a physical block address with the number of erase times which is small among spare blocks not allocated to the logical block addresses in the logical-physical conversion table, updates the number of erase times corresponding to the allocated physical block address, and updates the logical-physical conversion table.

Memory controller which effectively averages the numbers of erase times between physical blocks with high accuracy

A non-volatile storage device of the present disclosure includes non-volatile memory configured to have a plurality of areas for storing data, and a memory controller configured to write the data to the non-volatile memory and to read the data from the non-volatile memory. The memory controller includes a memory interface (I/F) connected to the non-volatile memory, a threshold calculator calculating a threshold for the number of error bits of the data based on a storage condition in the case of storing the data in the non-volatile memory without power, and a refresh controller determining whether refresh processing of the data is necessary, based on the threshold and the number of error bits of the data, and executing the refresh processing of the data if the refresh processing of the data is necessary.

Non-volatile storage device, non-volatile storage system, and memory control method with a refresh processing of a data

It is possible to accurately detect a physical block which has caused a fixture defect in a flash memory so as to limit the use of the physical block. By recording a history of generation of a physical block error and a history of physical erasing in an ECC error record, it is judged whether the error which has occurred is accidental or caused by a fixture defect. When no error is caused in the data written by physical erasing after a first read error occurrence, the first error is accidental and if another error is caused, the error is judged to be caused by a fixture defect. By using such an ECC error record, it is possible to accurately judge whether the error is accidental or caused by a fixture defect. By eliminating use of the physical block judged to have a fixture defect, it is possible to reduce read errors.

Nonvolatile storage device, memory controller, and defective region detection method

A host device includes a voltage source which is connected to a voltage line via a host voltage switch and which supplies a first voltage to the voltage line, a host regulator which is connected to the voltage line and which outputs the first voltage or a second voltage that is lower than the first voltage, a host IO driver for driving a data line with the output of the host regulator as a power source, a host voltage detection circuit for detecting whether the voltage of the data line is the second voltage or a voltage that is higher than the second voltage, and a host control unit for detecting a mismatch of interface voltages between the host device and a memory card based on the output voltage of the host regulator and the detection result of the host voltage detection circuit.

Information processing apparatus, nonvolatile storage device, information porcessing system and nonvolatile memory controller

A non-volatile storage device, which communicates with an access device and carries out reading and/or writing of data in accordance with a command from the access device, the device comprises one or more non-volatile memories for storing data and a memory controller for carrying out control of the non-volatile memory. The memory controller writes data to the error correcting group and writes a provisional error correcting code with respect to the data to the parity table if a data size is smaller than the first size when writing the data.

Non-volatile storage device and a memory controller controlling parity tables of recording regions of the non-volatile storage device

A non-volatile storage device comprises non-volatile memories for storing data; and a memory controller for carrying out control of the non-volatile memory. The memory controller stores second error correcting code as well as first error correcting code stored in the same page of the data. The memory controller, when writing data smaller than a predefined size, does not add the second error correcting code, and stores duplexed data of the data and the first correcting code in a different page. The memory controller, when reading, corrects data using the first and/or second correcting code. The valid data management table manages which logical block stores valid data with respect to an identical logical address.

Memory controller and non-volatile storage device

Upon copying data stored on a page in a copy source block of a nonvolatile memory to a page of a copy destination block, an access control unit of a memory controller copies data stored on a page associated with a first copy method to a page of the copy destination block after error correction by an error correction control unit copies data stored on a page associated with a second copy method to a page of the copy destination block without performing the error correction by the error correction control unit according to a copy mode stored in a copy mode storage area, and changes the copy mode associated with the copy destination block to a copy mode that is different from the copy mode of the copy source block.

Nonvolatile storage device performing periodic error correction during successive page copy operations

A memory controller includes a reading/writing control unit for controlling writing and reading of data to and from a physical block of a nonvolatile memory, a writing mode table for storing one of a first writing mode of protecting data against a power shutdown during writing and a second writing mode of writing data at a higher speed than the first writing mode, and a setting unit for setting the writing mode received from an access device in a writing mode table. The reading/writing control unit performs data writing based on the writing mode that has been set in the writing mode table.

Nonvolatile storage device, access device and nonvolatile storage system

The memory controller writes and reads data in and from a nonvolatile memory. The nonvolatile memory has a plurality of memory cell blocks, each memory cell block includes a plurality of multi-level cells each capable of storing m-bit data (m is a natural number of two or more), a first page to a m-th page are allocated to the respective m bits of the multi-level cell,

Nonvolatile memory device and memory controller

An access deviceincludes an access speed information partfor informing an access speed required for data recording by the access deviceto a nonvolatile memory deviceThe nonvolatile memory device includes an access condition determination partfor determining an access condition required for meeting the informed access speed and an access area determination unitfor determining an access area according to the determined access condition. The access deviceinforms the required access speed to the nonvolatile memory devicein advance so that the access condition determination partand the access area determination partin the nonvolatile memory devicerealize data recording which meets the access speed informed in advance upon the data recording. Thus, it is possible to access all the nonvolatile memory devices at a desired speed regardless of difference in characteristics of the recording speed of each of the nonvolatile memory devices.

Nonvolatile memory device, access device, and nonvolatile memory system

A non-volatile storage device includes one or more non-volatile memories for storing data, and a memory controller for carrying out the control of the non-volatile memory. The non-volatile memory includes the plurality of blocks, which are erase units, and the block includes the plurality of pages, which are write units of data, in each of the blocks at least one set of pages existing which include at least two pages sharing one word line. The memory controller configures a plurality of error correcting groups, each including at least one data page, which is a page for storing data, and at least one error correcting code page for storing a code for error correcting calculation of the data page, and assigns a page of a separate word line with respect to each of the data page and the error correcting page in the same error correcting group.

A flash memory unit includes a plurality of physical blocks including a plurality of memory cells and serving as erase units of data, wherein each of the memory cells is capable of recording information of 1 bit or more and degradation in the characteristics of the memory cells differs according to the amount of information that is recorded. A controller includes a control unit for controlling the reading, writing and erasure of data to and from the flash memory unit, and a degradation level table for recording a degradation level of the memory cells in physical block units. The control unit stores, in the degradation level table, the degradation level of the memory cells according to the amount of information stored in the memory cells for each cycle of data erasure from the physical blocks.

Nonvolatile memory controller and nonvolatile storage device

A nonvolatile memory system includes a memory card () and host equipment (). The memory card () includes a nonvolatile memory () including a plurality of physical blocks, and a memory controller () for writing data into the nonvolatile memory (). The host equipment () provides to the memory card () an access instruction that designates a logical address and a channel number. The memory controller () has an address conversion function for converting the logical address into a physical address in the nonvolatile memory (), a write destination determination function for determining in relation to the channel number a physical address in the nonvolatile memory () to which the data is to be written, and a channel management function for individually managing for each channel number a write state in which data of a smaller size than each physical block is written.

Memory controller, memory card, and nonvolatile memory system

A nonvolatile storage device includes a nonvolatile memory that stores data and a memory controller that controls the nonvolatile memory. The memory controller accepts a pause instruction to pause writing from the access device within a period in which data from the access device are written, and writes the data received from the access device to the nonvolatile memory within a predetermined time interval, then pauses the writing and accepts read and/or write of new data from the access device.

A nonvolatile storage device includes a controller and a nonvolatile memory. The controller has: a logical-physical address conversion part for converting a logical address designated by a host device into a physical address; and a boot code address conversion part for converting boot code address information designated by the host device into a physical address. After the power-on and before the logical-physical address conversion part becomes usable, a boot code is read from a part of region which can be accessed by designating a logical address from the host device by designating the boot code address information from the outside. Thus, it is possible to rapidly start the nonvolatile memory system after the power-on. In the state where the logical-physical address conversion part can be used, data-reading and data-writing are carried out by designating a logical address from the host device.

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Kyoto, Japan

Toshiyuki Honda