Synaptics Japan Gk

Synaptics Corporation

Toshiyuki Hikichi

Shinobu Nohtomi

Yasuhito Kurokawa

Masashi Takata

Shutaro Ichikawa

A processing system comprises a plurality of output terminals connectable to data lines of a display panel and a plurality of output amplifiers configured to output a plurality of drive voltages, respectively. The drive voltages have the same polarity. The processing system further comprises first switch circuitry configured to connect a first output terminal of the plurality of output terminals to a selected one of the plurality of output amplifiers.

Device and method for addressing unintended offset voltage when driving display panel

a display driver is provided which drives a display panel. The display driver includes first and second buffer amplifiers associated with first and second pixels positioned adjacent in a horizontal direction; first and second connection switches; and a controller. Each of the first and second buffer amplifiers includes: a differential input circuit including a MOS transistor pair, first and second drain interconnections; an active load circuit connected to the first and second drain interconnections; and an output stage. The first connection switch is connected between the output nodes of the first and second buffer amplifiers. The second connection switch is connected between the first drain interconnections of the first and second buffer amplifiers. The controller controls the first and second switches in response to image data associated with the first and second pixels.

Drive circuitry configuration in display driver

The display device includes display drivers including first and second ones operable to output, based on display data, gradation signals to source lines of display panel regions. The display device is arranged to be able to suppress the variation in output voltage between display drivers while minimizing the increases in chip area of the display drivers and in wiring area of a display panel and keeping high noise resistance. Each display driver can generate gray scale reference voltages for producing gradation signals corresponding to display data. The first display driver can sequentially transmit gray scale reference voltages generated by itself to the second display driver. Based on the transmitted gray scale reference voltages, the second display driver makes the first display driver execute calibration for decreasing the absolute value of difference between gray scale reference voltages generated by the first and second display drivers, or executes the calibration by itself.

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Tokyo, Japan

Toshiyuki Hikichi