Kabushiki Kaisha Toshiba

Kioxia Corporation

Toshiyuki Furusawa

Masahiro Kanazawa

Naoyuki Kawabe

Kimiyoshi Usami

Masayuki Koizumi

Hidemasa Zama

Daisuke Sonoda

Kenji Sakaue

Mototsugu Hamada

Shinya Takeda

Tsuyoshi Nishikawa

Katsuhiro Seta

Yusei Itaya

Masaru Ozeki

Masaaki Yamada

Takeshi Kitahara

Koichi Mori

Takeshi Yoshimoto

Isao Ooigawa

Yukiko Ito

Munehito Mushiga

Nariyuki Fukuda

Noriyuki Moriyasu

Eiji Sawada

Satoko Kawakami

Hitoshi Nemoto

Hiroyuki Fujioka

Tokio Tanaka

According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.

Memory system

According to one embodiment, a semiconductor integrated circuit includes a semiconductor integrated circuit a voltage regulator providing a prescribed power-supply voltage, a plurality of delay test circuits, each of the delay test circuits being configured in each of areas where electrical current flows in response to each of operation modes, a test control unit executing a delay test using the delay test circuit under a test mode while decreasing a power-supply voltage in a stepwise fashion, a supply voltage decision unit deciding the power-supply voltage of the operation mode on a basis of the delay test, a memory unit storing the power-supply voltage of each operation mode, a supply voltage configuration unit reading out the power-supply voltage corresponding to the operation mode from the memory unit, and the supply configuration unit arranging the power-supply voltage as an output voltage of the voltage regulator when each of the operation modes starts to execute.

Semiconductor integrated circuit deciding a power-supply voltage based on a delay test

A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal from a previous stage is inputted as an input signal, and an output terminal. A first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state. A second conductivity-type second MIS transistor cuts off a leakage current of the MIS transistor in the standard cell.

Semiconductor integrated circuit device

A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells has: a standard cell which includes a MIS transistor, the standard cell including an input terminal to which an output signal from a previous stage is inputted as an input signal and an output terminal, and the standard cell performing a predetermined logic operation based on the input signal and outputting a result of the logic operation as an output signal from the output terminal; a first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state; and a second conductivity-type second MIS transistor which is provided between the standard cell and a second power supply voltage, the second MIS transistor including a control terminal to which the circuit control signal is inputted, and the second MIS transistor cutting off a leakage current of the MIS transistor in the standard cell based on the circuit control signal in order to bring the standard cell into the operation-stopped state.

An automatic circuit design apparatus includes a setting module configured to set an upper limit electric potential of a virtual ground line in a circuit to be designed, by use of a cell library for low-threshold cells, a cell library for high-threshold cells, and information of the circuit to be designed. A layout generator is configured to generate a layout based on the information, the cell library for low-threshold cells, and the cell library for high-threshold cells.

Automatic circuit design apparatus, method for automatically designing a circuit, and computer program product for executing an application for an automatic circuit design apparatus

A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

Semiconductor integrated circuit with reduced leakage current

Semiconductor integrated circuit

Semiconductor integrated circuit, logic operation circuit, and flip flop

A digital signal processor (DSP) of high speed and high precision is disclosed. The DSP (i.e., digital arithmetic integrated circuit) comprises: an arithmetic data storing memory ( ) for storing arithmetic data and for outputting, in one instruction cycle, first and second arithmetic data strings each composed of a plurality of bits, the first arithmetic data string being composed of m-bits of at least a predetermined unit word length and the second arithmetic data string being composed of (m&times;n)-bits of a unit word length; two arithmetic operand storing registers ( ) for storing the first and second arithmetic data strings outputted by said arithmetic data storing memory, respectively; an arithmetic logical unit for executing arithmetic operation on the basis of the two operands outputted by said arithmetic operand storing registers in one instruction cycle ( ); and an arithmetic result storing register ( ) for storing the arithmetic results outputted by said arithmetic logical unit.

Digital arithmetic integrated circuit

Semiconductor circuit having a combination circuit being switched between an active and inactive state

Growing community of inventors

Tokyo, Japan

Toshiyuki Furusawa