Nec Corporation

Nippon Electric Co., Ltd.

Toshiya Takahashi

Junichi Iwasaki

Yoshikuni Sato

Hisao Harigai

Tamotsu Iwasaki

A rounding unit for use in arithmetic processing of register floating point data. The rounding unit comprises a mantissa part register for storing the mantissa part of the floating point data, an exponent part register for storing the exponent part of the floating point data, a judging circuit for judging whether the rounding operation is raising or truncating, a mantissa part incrementer for incrementing the mantissa part of the floating point data and outputting a carry signal when it is overflowed, an exponent part incrementer for incrementing the exponent part of the floating point data and a selection circuit which, in response to the carry signal from the mantissa part incrementer and the judging signal from the judging circuit, orders the mantissa part register to store a constant data of which the most significant bit is '1' and the other bits are '0', when the rounding operation is raising and the carry signal is present. For generating the constant data, a constant register or an adjusting means is employed. The rounding unit executes the rounding operation of floating point data by hardware and thus it operates at a very high speed.

Rounding unit for use in arithmetic processing of floating point data

A normalizing circuit is disclosed which can make bit shift operation for a bit string. The normalizing circuit has a leading 'one' detector, an encoder and a bit shifter. The leading 'one' detector detects a bit position of a leading 'one' among a bit string and produces a signal to indicate the bit position of the leading 'one'. The encoder produces a control signal by which bit shift operation is executed. The bit shifter has a plurality of shift paths to shift leftwardly or rightwardly the bit string such that the leading 'one' bit is positioned at the most left position or the most right position. One of the plurality of shift paths is selected by the control signal produced by the encoder. Thus, bit shift operation of the leading 'one' bit can be executed at a high speed.

Normalizing circuit

An information processing apparatus with an instruction prefetch unit is disclosed, in which a CPU operation can be stopped at a desired address in response to a break signal. The instruction prefetch unit has an instruction prefetch circuit storing an instruction and an indication register storing the break signal. A read operation and a write operation of the indication register are executed together with those of the instruction prefetch circuit. Thus, a break point can be set a desired address by using the indication register, and the break operation can be correctly preformed without the need for complex hardware.

Information processing apparatus having an instruction prefetch circuit

A data processing system including a central processing unit (CPU), a memory device operating on a data word length of 2 m-bits, an input/output device operating on a data word length of m bits, an m-bit register and a direct memory access (DMA) controller for transferring data words in both directions between the memory device and the input/output device independently of the CPU. A 2 m-bit bus is connected between the memory device and two m-bit buses connected to a bus switching circuit which controls the transfer of m-bit data words between the 2 m-bit bus and the register and the input/output device. A control circuit generates timing and switching signals such that, during a first bus cycle a first m-bit data word from the input/ouput device is stored in the register, and during a second bus cycle a second m-bit data word from the input/output device is transferred directly via the buses to the memory device and, also, the first m-bit data word, stored in the register, is transferred to the memory device. For transfer of a data word from the memory device to the input/output device, during a first bus cycle m bits of data are transferred directly via the buses to the input/output device and, also, the following m bits are stored in the register, and during a second bus cycle the following m bits are transferred to the input/output device.

Growing community of inventors

Tokyo, Japan

Toshiya Takahashi