Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Toshiya Miyo

Satoshi Eto

Toshikazu Nakamura

Kuninori Kawabata

Ayako Sato

Takaaki Suzuki

Masafumi Yamazaki

Yasuhiro Onishi

Takayuki Yoneda

Noriko Kawamura

Masato Matsumiya

Akira Kikutake

Atsumasa Sako

Junichi Sasaki

Yuji Serizawa

A semiconductor storage device includes a memory cell array in which a memory cell including an MOS capacitor is arranged; a power supply unit that supplies a plate voltage to a plate line that is coupled to a gate electrode of the MOS capacitor; and a switch that couples the plate line to a first power supply line when an access to the memory cell array is caused.

Semiconductor storage device

The data memory cell array and parity memory cell array in the memory cell array has a constitution that is capable of corresponding with a plurality of ECC code lengths. An input-side parity generation circuit that generates parities from write data, an output-side parity generation circuit that generates parities from read data, and a syndrome generation circuit that generates a syndrome bit that indicates an error bit from the read parity bits and generated parity bits are constituted so as to be capable of switching, according to the plurality of ECC code lengths.

Semiconductor memory device capable of changing ECC code length

A memory controller connected to memory includes: an address reception unit for receiving an address code externally input together with a command; and a command conversion unit for outputting to the memory an MRS command to change the internal settings of the memory based on the address code when the address code input together with a first command specifies an address space for which the memory is not implemented.

Memory controller, semiconductor memory, and memory system

A semiconductor memory for inputting and outputting data synchronously with a clock includes a clock reception unit for receiving the clock, and a command reception unit for initially receiving a first specific command synchronizing with the clock after turning a power on, after a low-power standby or after an initialization, followed by starting a command reception.

Semiconductor memory, memory controller and control method for semiconductor memory

An external terminal receives an external signal so as to access the first and second memory chips. The test starting terminal receives a test starting signal activated when the first or second memory chip is tested and inactivated when the first and second memory chips are normally operated. The access signal generator converts the external signal to a memory access signal of the first memory chip. The first selector selects the external signal, which is a test signal, during activation of the test starting signal, selects the memory access signal during the inactivation of the test starting signal. That is, during the test modes, the first memory chip can be directly accessed from the exterior. For this reason, the test program for testing the first memory chip alone can be diverted as the test program following an assembly of the semiconductor device.

Semiconductor device

Regular data inputted/outputted to/from external terminals is read/written to/from a regular cell array, and parity data is read/written from/to a parity cell array. Since the parity data is generated by a parity generation circuit, it is difficult to write a desired pattern to the parity cell array. The regular data and the parity data are exchanged with each other by a switch circuit, so that the regular data can be written to the parity cell array and the parity data can be written to the regular cell array. This enables the write of desired data to the parity cell array. A test of the parity data can be easily conducted. In particular, a leakage test or the like between memory cells can be easily conducted.

Semiconductor memory having an error correction function

Second memory cells of a second memory block each have an area 2times (a is a positive integer) that of each first memory cell of a first memory block. Sizing the first and second memory cells in a predetermined ratio can make easily identical the dimensions of the first memory block and the second memory block. Consequently, it is possible to easily align peripheral circuits to lie around the plurality of first and second memory blocks, such as decoders. This also facilitates the wiring of signal lines to be connected to the peripheral circuits. This makes it possible to improve the layout design efficiency for a semiconductor integrated circuit. Thus, a plurality of types of memory blocks can be formed on a semiconductor integrated circuit efficiently. The semiconductor integrated circuit can be prevented from increasing in chip size depending on the layout design, owing to its simplified layout.

Semiconductor integrated circuit

A timer measures a predetermined time from the reception of an external access signal, and outputs an access request signal after the predetermined time has elapsed. The external access signal causes a memory core to execute a read operation, and the access request signal causes the memory core to operate. The predetermined time is set to be longer than a core operation time for the memory core to perform a single operation. The memory core thus performs no operation when the external access signal varies in a time shorter than the predetermined time. Consequently, it is possible to prevent the memory core from malfunctioning and data retained therein from crashing even when external access signals are supplied at intervals at which the memory core is unable to properly operate.

Semiconductor memory

A logic chip and a memory chip to be accessed by the logic chip are mounted in a single package. A pattern generator of the logic chip operates during a first test mode to generate internal test pattern for the memory chip. A pattern selector selects, during the first test mode, the internal test pattern outputted from the pattern generator, selects, during a second test mode, an external test pattern supplied via a test terminal, and outputs the selected test pattern to the memory chip. The memory chip mounted in the package is tested by use of, in accordance with a mode selecting signal, either the internal test pattern in the first test mode, generated within the logic chip, or the external test pattern in the second test mode, supplied from the exterior.

A semiconductor memory with a memory core for dynamically holding data in which a data collision at the time of the semiconductor memory making the transition from a standby state to a nonstandby state is prevented. A first buffer circuit inputs an enable signal for controlling a standby state or a nonstandby state. A second buffer circuit outputs a predetermined logic signal or a read/write signal for controlling the reading of data from or the writing of data to the memory core in accordance with the enable signal. A third buffer circuit outputs an inverted signal obtained by inverting the logic signal or the read/write signal in accordance with the enable signal. A control circuit controls the reading or writing of the data by the read/write signal outputted from the second buffer circuit. A data output control circuit controls the inputting of the data from or the outputting of the data to the outside by the inverted signal or the read/write signal outputted from the third buffer circuit.

A semiconductor memory device includes a first bit line connected to a memory cell via a transistor, a transfer gate, a second bit line connected to the first bit line via the transfer gate, a sense amplifier connected to the second bit line, a first precharge circuit for precharging the first bit line, a second precharge circuit for precharging the second bit line, a control circuit which precharges the first bit line by the first precharge circuit after closing the transfer gate, followed by subsequent precharging of the second bit line by the second precharge circuit.

DRAM operating like SRAM

In the first and second regions data not concurrently transferred is transferred by using data lines having the respective different wiring layers. The vertical positions of the data lines are reversed between the first and second regions. In the switching regions the data lines are exchanged between the first and second regions. The parasitic capacitances associated with the two data lines are practically equal to each other so that the delay times of signals transferred along the data lines are equal to each other. This can prevent a circuit malfunction due to a parasitic capacitance difference. In the semiconductor integrated circuit where memory cell arrays and sense amplifier arrays are alternately wired, forming the first and second regions over the memory cell arrays and the switching regions over the sense amplifier arrays makes it easier to exchange the vertical positions of the data lines in the switching regions.

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Kawasaki, Japan

Toshiya Miyo