Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kabushiki Kaisha Tosbhia

Toshiya Kotani

Satoshi Tanaka

Soichi Inoue

Hiromitsu Mashita

Chikaaki Kodama

Shigeki Nojima

Fumiharu Nakajima

Koji Hashimoto

Takafumi Taguchi

Kyoko Izuha

Ryota Aburada

Hirotaka Ichikawa

Shoji Mimotogi

Sachiko Kobayashi

Ayako Nakano

Suigen Kyoh

Kazuya Fukuhara

Tadahito Fujisawa

Taiga Uno

Hidefumi Mukai

Hiroko Nakamura

Kazuhito Kobayashi

Kazuyuki Masukawa

Yasunobu Kai

Shinichi Ito

Takashi Sato

Takuya Futatsuyama

Yuichiro Yamazaki

Kei Hayasaki

Takeshi Ito

Shinji Yamaguchi

Ichiro Mori

Akiko Mimotogi

Seiro Miyoshi

Takaki Hashimoto

Susumu Watanabe

Yukiyasu Arisawa

Ryuji Ogawa

Toru Mikami

Katsumi Iyanagi

Yuko Kono

Tetsuaki Matsunawa

Koichi Nakayama

Michiya Takimoto

Atsushi Maesono

Taiki Kimura

Koji Asakawa

Kosuke Yanagidaira

Kenji Yoshida

Masanori Takahashi

Shigeki Hattori

Fumihiro Minami

Tatsuhiko Higashiki

Takashi Obara

Takashi Nakazawa

Kazuko Yamamoto

Osamu Ikenaga

Atsushi Watanabe

Shimon Maeda

Yuji Setta

Masaki Satake

Shigeru Hasebe

Masahiro Miyairi

Mitsuhiro Yano

Masanari Kajiwara

Hirotaka Ichiakwa

Hiromitusu Mashita

Satomi Nakamura

Ayako Endo

Shinichiroh Ohki

According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and a plurality of second patterns extending in the first direction and arranged at a center between the first patterns, respectively, are provided; and drawing a connecting portion which extends in the second direction and connects two neighboring first patterns sandwiching one of the second patterns, and separating the one of the second patterns into two patterns not contacting the connecting portion.

Method of wiring layout, semiconductor device, program for supporting design of wiring layout, and method for manufacturing semiconductor device

According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1)second sidewall film matching a pattern of a n(where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer. A first dimension matching an interconnect width of the interconnects and an interconnects interval in the element formation area is (k1/2)&#xd7;(&#x3bb;/NA) or less when an exposure wavelength of an exposure device is &#x3bb;, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1. A second dimension matching an interconnect interval in the drawing area is greater than the first dimension.

Semiconductor device having contacts in drawing area and the contacts connected to word lines extending from element formation area

A microstructure body according to an embodiment includes a stacked body. The stacked body includes a plurality of unit structure bodies stacked periodically along a first direction. A configuration of an end portion of the stacked body in a second direction is a stairstep configuration including terraces formed every unit structure body. The second direction intersects the first direction. A first distance in a third direction between end edges of two of the unit structure bodies facing the third direction is shorter than a second distance in the second direction between end edges of the two of the unit structure bodies facing the second direction. The third direction intersects both the first direction and the second direction.

Microstructure device and method for manufacturing the same

According to an embodiment, a pattern data generation method is provided. In the pattern data generation method, when a resist on a substrate is exposed using a mask, an optical image at a designated resist film thickness position is calculated using a mask pattern. Feature quantity related to a shape of a resist pattern at the resist film thickness position is extracted, based on the optical image. Also, whether the resist pattern is failed is determined, based on the feature quantity, and pattern data of a mask pattern determined as failed is corrected.

Pattern data generation method, pattern verification method, and optical image calculation method

A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern.

Method of fabricating semiconductor device and semiconductor device

One embodiment includes: a step of evaluating an amount of flare occurring through a mask at EUV exposure; a step of providing a dummy mask pattern on the mask based on the evaluated result of the amount of flare; and a step of executing a flare correction and an optical proximity correction on a layout pattern. The layout pattern is provided by the EUV exposure through the mask with the dummy mask pattern.

Pattern generating method, pattern forming method, and pattern generating program

According to one embodiment, a pattern including first and second block phases is formed by self-assembling a block copolymer onto a film to be processed. The entire block copolymer present in a first region is removed under a first condition by carrying out energy beam irradiation and development, thereby leaving a pattern including the first and second block phases in a region other than the first region. The first block phase present in a second region is selectively removed under a second condition by carrying out energy beam irradiation and development, thereby leaving a pattern including the first and second block phases in an overlap region between a region other than the first region and a region other than the second region, and leaving a pattern of second block phase in the second region excluding the overlap region. The film is etched with the left patterns as masks.

Pattern forming method

Method of manufacturing semiconductor device using sidewall films for pitch multiplication in forming interconnects

According to one embodiment, a production method for a mask layout of an exposure mask includes evaluating a candidate layout by comparison between an imaged image group and a reference image group. The imaged image group is composed of a plurality of imaged images of patterns formed by performing lithography under a plurality of levels of exposure condition using the candidate layout. The reference image group is composed of a plurality of reference images produced by simulation on assumption of a plurality of levels of the exposure condition.

Production method and evaluation apparatus for mask layout

According to one embodiment, a semiconductor device includes a plurality of wires arranged in parallel at a predetermined pitch, a plurality at first contacts that are each connected to an odd-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to a wiring direction of the wires, and a plurality of second contacts that are each connected to an even-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to the wiring direction of the wires in such a way as to be offset from the first contacts in the wiring direction of the wires, in which the first contacts are offset from the second contacts by a pitch of the wires in an orthogonal direction with respect to the wiring direction of the wires.

Semiconductor device and manufacturing method of semiconductor device

According to a sub-resolution assist feature arranging method in embodiments, it is selected which of a rule base and a model base is set for which pattern region on pattern data corresponding to a main pattern as a type of the method of arranging the sub-resolution assist feature for improving resolution of the main pattern formed on a substrate. Then, the sub-resolution assist feature by the rule base is arranged in a pattern region set as the rule base and the sub-resolution assist feature by the model base is arranged in a pattern region set as the model base.

Sub-resolution assist feature arranging method and computer program product and manufacturing method of semiconductor device

In the method of correcting a mask pattern according to the embodiments, a mask pattern correction amount for a reference flare value is calculated as a reference mask correction amount, for every type of patterns within the layout, and a change amount of the mask pattern correction amount corresponding to the change amount of the flare value is calculated as the change amount information. A mask pattern corresponding to the flare value of the pattern is created based on the reference mask correction amount and the change amount information corresponding to the pattern, extracted from the information having the pattern, the reference mask correction amount, and the change amount information correlated with each other, and based on a difference between the flare value of the pattern and the reference flare value.

Method of correcting mask pattern, computer program product, and method of manufacturing semiconductor device

A method of manufacturing a semiconductor device, which forms a pattern by performing pattern transformation steps multiple times, comprises setting finished pattern sizes for patterns to be formed in each consecutive two pattern transformation steps among the plurality of pattern transformation steps based on a possible total amount of in-plane size variation of the patterns to be formed in the consecutive two pattern transformation steps.

Method of manufacturing semiconductor device and computer readable medium for storing pattern size setting program

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Machida, Japan

Toshiya Kotani