Panasonic Corporation

Toshiya Kogishi

Toshinobu Hatano

Kenji Arakawa

Toshiyuki Nakashima

Jun Kajiwara

Toshiya Fujii

Satoshi Fukumoto

Koji Yamada

Yoshihisa Shimazu

Ryouichi Nagayoshi

A semiconductor integrated circuit () fetches read data from DDR-SDRAMs () each operating in synchronization with a clock, and transfers the read data. The semiconductor integrated circuit () includes read buffers () for fetching the read data from the DDR-SDRAMs (), and transferring the read data, latch timing control circuits () for controlling respective latch timings with which the read buffers () fetch the read data from the DDR-SDRAMs () based on respective data strobe signals from the DDR-SDRAMs (), and a read timing control circuit () for controlling respective read timings with which the read buffers () transfer the read data based on the latch timings of the latch timing control circuits ().

Semiconductor integrated circuit for fetching read data from a DDR-SDRAM operating in synchronization with a clock

A solid-state image sensing apparatus including a solid-state image sensing device and a signal processing circuit. The solid-state image sensing device includes: a vertical transfer unit, composed of transfer columns corresponding to columns of the light-to-electric conversion elements, operable to transfer, in a vertical direction, signal charges read out from the light-to-electric conversion elements; a horizontal transfer unit operable to receive the signal charges from the vertical transfer unit and transfer them in a horizontal direction. The signal processing circuit converts the signal charges from the horizontal transfer unit into pixel data, and rearranges it into a two-dimensional array. In the rearrangement, the signal processing circuit, per transfer of one piece of pixel data, cyclically selects a line memory out of three line memories, writes a piece of pixel data into the selected line memory, or reads a row of pixel data from the selected line memory.

Pixel arranging apparatus, solid-state image sensing apparatus, and camera

An interface circuit is provided for use in a semiconductor device which transmits and receives a signal to and from the outside. The interface circuit includes a signal input/output terminal for receiving a signal from the outside in a signal input mode and a signal from the semiconductor device in a signal output mode, an input buffer gate circuit having an input terminal connected to the signal input/output terminal and for outputting a signal received at the input terminal to the semiconductor device, and an input level control circuit for fixing a potential level at the input terminal of the input buffer gate circuit to a predetermined level in a signal no-supply mode and removing the fixation of the potential level in the signal output mode and in the signal input mode.

Interface circuit

A charge transfer implemented by a transfer section for transferring charges stored in image sensor elements along one direction on a surface where the image sensor elements are disposed is halted for a predetermined length of time. The charges are transferred from the transfer section without reading the charges from the image sensor elements after the charge transfer is halted for the predetermined length of time. A position where a defect is generated in an image pickup sensor is identified based on signal levels of the transferred charges. A defective signal level of the image pickup sensor generated on a line including the defect-generating position and in parallel with the one direction is corrected. As a result of the foregoing process, a display failure is precisely corrected.

Growing community of inventors

Kyoto, Japan

Toshiya Kogishi