Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Other

Lg Electronics Inc.

Hatachi Ltd

Toshitsugu Takekuma

Akira Yamagiwa

Ryoichi Kurihara

Masamichi Ishihara

Hidetoshi Iwai

Masaya Umemura

Kazuya Ito

Takashi Moriyama

Toshio Suzuki

Hideki Osaka

Kenji Kashiwagi

Yutaka Ito

Takehisa Hayashi

Toshiro Takahashi

Toshiyuki Sakuta

Kenichi Ishibashi

Masao Inoue

Asayoshi Kawashita

Shigetoshi Sakomura

Masanori Tazunoki

Tsutomu Goto

Haruo Ii

Wataru Arakawa

Shozo Satake

Tatsuhiro Aida

Sigeru Kaneko

Ii: Haruo

A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between the driving and receiving circuit blocks. The inter-block transmission line is terminated by a resistor having substantially the same impedance as the interblock transmission line. The intra-block transmission lines are provided with a resistance element having a resistance substantially equal to a value derived by subtracting half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.

Signal transmitting device suited to fast signal transmission

A signal transmission system includes a first circuit block having a first output circuit for producing a first signal, a plurality of second circuit blocks each including a first receiving circuit for receiving the first signal, and transmission lines connected between the first circuit block and the second circuit blocks, wherein the first circuit block further includes a second output circuit for producing a second signal, and wherein each of the second circuit blocks further includes a second receiving circuit for receiving the second signal, the first receiving circuit latching the first signal in synchronism with the second signal, removing the unsuccessfulness in the signal transmission and reception due to the propagation delay of signals between circuits.

Signal transmission system

A signal transmitting circuit includes one or more circuit blocks having a driving circuit and an intra-block transmission line for transmitting a signal produced by the driving circuit, one or more circuit blocks having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between both of the driving and receiving circuit blocks. Inter-block transmission line is terminated at one or two ends by one or two resistors having substantially the same impedance as the interblock transmission lien itself. Each of the intra-block transmission line is provided with a resistance element having a resistance equal to or close to a value derived by subtracting a half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.

Circuit module connected to a transmission line including arrangement to suppress reflections at a branch point of the transmission line

Semiconductor memory

A signal transmitting circuit includes one or more circuit blocks having a driving circuit and an intra-block transmission line for transmitting a signal produced by the driving circuit, one or more circuit blocks having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between both of the driving and receiving circuit blocks. Inter-block transmission line is terminated at one or two ends by one or two resistors having substantially the same impedance as the interblock transmission line itself. Each of the intra-block transmission line is provided with a resistance element having a resistance equal to or close to a value derived by subtracting a half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.

Signal transmitting device, circuit block and integrated circuit suited to fast signal transmission

There are provided plural synchronous RAMs, a memory controller, a bus for inputting the signal output from the memory controller 1a to the synchronous RAMs, and a bus for inputting the signals output from the synchronous RAMs to the memory controller. Each of the buses has a main line and two stub lines connected to the trunk like. Each of the synchronous RAMs is connected to the corresponding stub line so that the sum of the bus length of the bus between the synchronous RAM and the memory controller and the bus length of the bus between the synchronous RAM and the memory controller is substantially constant among all of said synchronous RAMs. Therefore, the signal transmission time between the bus master and the plural bus slaves can be shortened without increasing the number of pins of the bus master while keeping the signal transmission time substantially constant among the plural bus slaves.

Bus system, printed circuit board, signal transmission line, series

A synchronous data transfer system includes an oscillation circuit and a plurality of nodes connected to the oscillation circuit and each including at least an internal logic circuit. Each of the nodes outputs a phase reference signal indicating phase of the clock signal, data processed by the internal logic circuit provided internally of the node. The system further includes a transfer end signal indicating an end of the data transfer, in synchronism with the clock signal, and a phase reference signal bus connected to each of the plural nodes, a data bus connected to each of the plural nodes for transmitting the data and a transfer end signal bus connected to each of the plural nodes for transmitting the transfer end signal. A sender node of the plural nodes includes sending unit for sending the data to a receiver node of the plural nodes with a delay relative to the phase reference signal which the sender node itself sent onto the phase reference signal bus while sending simultaneously the transfer end signal to the receiver node, whereas the receiver node includes at least a selecting unit for converting the phase reference signal received into phase information to thereby select a clock signal having a predetermined phase with the clock signal received by the receiver node and a receiving unit for receiving the data from the sender node by using the selected clock signal.

Synchronous data transfer system

A source-clock-synchronized memory system having a large data storage capacity per memory bank and a high mounting density. The invention includes a memory unit having a first memory riser board B1 mounted on a base board through a first connector C1 and a second memory riser board B2 mounted on the base board BB through a second connector C2. The first memory riser board has a plurality of first memory modules mounted on the front surface thereof and the second memory riser board has a plurality of second memory modules mounted on the front surface thereof. The first and second memory riser boards are arranged in such a way that the back surface of the first memory riser board faces the back surface of the second memory riser board. The invention further includes a board linking connector for connecting signal lines on the first memory riser board to corresponding signal lines on the second memory riser board.

Source-clock-synchronized memory system and memory unit

A synchronous data transfer system includes an oscillation circuit and a plurality of nodes connected to the oscillation circuit. Each node includes at least an internal logic circuit. Each of the nodes outputs a phase reference signal indicating phase of the clock signal, data processed by the internal logic circuit in response to the phase reference signal, and a transfer end signal indicating an end of transferring the data, respectively, in synchronism with the clock signal. A phase reference signal bus is connected to each node. A data bus is connected to each node for transmitting the data and a transfer end signal bus is connected to each node for transmitting the transfer end signal. A sender node includes a sending unit for sending data to a receiver node with a delay after the phase reference signal transmitted to the phase reference signal bus by the sender node, and sending simultaneously the transfer end signal to the receiver node. The receiver node includes a selecting unit for converting the phase reference signal into phase information to select a clock signal having a predetermined phase based on the received clock signal and a receiving unit for receiving data from the sender node using the selected clock signal.

In a simultaneous bidirectional transmission circuit for conducting simultaneous two-way communication between LSIs via a transmission line, an input/output circuit connected to the transmission line is included in an LSI. The input/output circuit has a driver and a receiver. The driver sends out an output signal depending on a logical signal within the LSI to the transmission line. The receiver receives a mixed signal having a mixture of a received signal and the output signal via the transmission line. The signal to be received by the receiver in an LSI has been sent out to the transmission line by the other party i.e., another LSI in communication therewith. The receiver receives the logical signal output as well. The receives derives a difference between the mixed signal and the logical signal output, thereby removing the component of the logical signal from the mixed signal, and outputs the received signal. The receiver has a reference circuit for receiving the logical signal and outputting it to a bias circuit, a bias circuit for generating a divided voltage signal in conjunction with internal resistance of the reference circuit, and a differential receiver for receiving the mixed signal and the divided voltage signal and outputting the difference between them. The reference circuit and the bias circuit are formed by using MOS transistors.

Simultaneous bidirectional transmission circuit

Growing community of inventors

Ebina, Japan

Toshitsugu Takekuma