Matsushita Electric Industrial Co., Ltd.

Panasonic Liquid Crystal Display Co., Ltd.

Pasona Knowledge Partner Inc.

Panasonic Corporation

Toshitaka Uchikoba

Kiyoto Ohta

Makoto Arita

Keisuke Izawa

Tomonori Fujimoto

Yuji Yamasaki

Kenichi Origasa

Hiroyuki Sadakata

A liquid crystal display panel to be used in a vertical orientation includes: a first substrate; a second substrate located opposite to the first substrate; and a liquid crystal layer disposed between the first substrate and the second substrate. When a position of a top end of the liquid crystal layer is defined as a first position and a position of a bottom end of the liquid crystal layer is defined as a second position when the liquid crystal display panel is placed in the vertical orientation, a distance between the first substrate and the second substrate when the liquid crystal panel is in a horizontal orientation gradually decreases from the first position to the second position.

Liquid crystal display panel and liquid crystal module

A method of setting a common electrode voltage of a liquid crystal display panel in a liquid crystal module is provided. The liquid crystal module includes the liquid crystal display panel including an alignment film, and a backlight disposed behind the liquid crystal display panel. The method of setting a common electrode voltage of a liquid crystal display panel includes: eliminating an electric charge of the alignment film by turning on the backlight without driving the liquid crystal display panel to emit light of the backlight onto the liquid crystal display panel; and setting the common electrode voltage of the liquid crystal display panel by adjusting the common electrode voltage, after the eliminating of the electric charge.

Method of setting common electrode voltage of liquid crystal display panel, and liquid crystal module

In a semiconductor memory, a sub bit line hierarchical switch is provided correspondingly to each sub bit line between the sub bit line and a main bit line corresponding to the sub bit line, and a complementary sub bit line hierarchical switch is provided correspondingly to each complementary sub bit line between the complementary sub bit line and a complementary main bit line corresponding to the complementary sub bit line. Furthermore, the semiconductor memory includes a hierarchical switch control unit for turning off all the sub bit line hierarchical switch and the complementary sub bit line hierarchical switch when a given signal is input.

Semiconductor memory and test method for the same

A semiconductor apparatus according to the present invention comprises a current source increasing a current volume in compliance with a rise of a temperature and an oscillation circuit driven by the current of the current source and outputting a clock for refresh control. The semiconductor apparatus, preferably, further comprises a memory device performing the refresh in synchronization with the output clock of the oscillation circuit or the divided clock thereof. The semiconductor apparatus, preferably, further comprises a constant voltage source generating a constant voltage using the current source, an oscillation circuit using the current of the current source, and a memory using the constant voltage generated by the constant voltage source as a reference voltage for a power supply circuit and performing the refresh in synchronization with the output clock of the oscillation circuit or the divided clock thereof.

Semiconductor apparatus capable of performing refresh control

A semiconductor integrated circuit device includes a charge pump circuit for outputting a predetermined negative voltage to a negative voltage node, a voltage detection circuit for generating a first detection signal when the voltage of the negative voltage node has reached a first detection voltage and for generating a second detection signal when the voltage of the negative voltage node has reached a second detection voltage, an oscillator that is driven in response to the first detection signal so as to generate a signal for driving the charge pump circuit, and a negative voltage raising circuit that has an output terminal connected to the negative voltage node, and that is driven in response to the second detection signal so as to raise the voltage of the negative voltage node through the output of its output terminal. The VBB voltage can be increased rapidly and can be controlled at higher speeds, thereby increasing the stability of the voltage.

Semiconductor integrated circuit device and method of manufacturing the same

Each of a plurality of sense amplifiers in a sense amplifier drive circuit of a DRAM includes a PMOS sense amplifier drive transistor and an NMOS sense amplifier drive transistor. The source of each of the PMOS sense amplifier drive transistors is connected to a first common power line and to multiple independent power lines orthogonal thereto. The source of each of the NMOS sense amplifier drive transistors is connected to a first common power line and to multiple independent power lines orthogonal thereto. Therefore, charging current and discharging current are distributed to the multiple power lines arranged in mesh-like pattern. Therefore, in sensing operations, the charging and the discharging currents in bit lines are distributed so that interference between the sense amplifiers can be suppressed and the data read-out speed can be increased.

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Hyogo, Japan

Toshitaka Uchikoba