Sony Corporation

Toshitaka Senuma

Tokuya Fukuda

Toru Shiono

Katsumi Matsuno

Satoshi Nojima

Takashi Kohashi

Noriyuki Yamashita

Isao Masuda

Shinji Takada

Yoshinori Tomita

Kenta Tanaka

Futao Yamaguchi

Koji Okumoto

Keiko Ishihama

A sampling phase of digital data is converted with having a phase stabilization and a phase alignment. In a converting circuit for converting first digital data synchronized with a fist clock into second digital data synchronized with a second clock not synchronized with the first clock, there are provided; a dividing circuit for dividing 1 (one) time period of the first clock into N time periods ('N' being larger than, or equal to 2); a coefficient setting circuit for setting first and second interpolation coefficients with respect to each of the divided time periods; a data producing circuit for producing the second digital data from data within a certain clock period and data within another clock period subsequent to the certain clock period among the first digital data by using the first and second interpolation coefficients in the divided period where the second clock is located, among the first and second interpolation coefficients set for each of the divided periods.

Circuit for converting sampling phase of digital data

A video camera including a zoom-up lens assembly magnifying an image, a charge coupled device picking up the magnified image, a recording medium for storage of the magnified image and a viewfinder having a display panel and a liquid crystal device for determining a partial area of the display panel on which the magnified image to be recorded is displayed. The liquid crystal device is controlled by a microcomputer so as to form an opaque frame-like line surrounding the partial area of the display panel.

Video camera having an improved zoom system

A method of testing an electronic apparatus which eliminates a control signal line for setting an integrated circuit to a test mode and a test mode select terminal of an external terminal section and wherein fetching of test data and transfer of the thus fetched test data are performed in an integrated operation. In each of the integrated circuits, a boundary scan control circuit discriminates a category code at the top of data inputted from a serial input terminal to control a pair of switching circuits. When the category code represents a test mode, predetermined terminals of the switching circuits are selected so that input data are sent out to boundary scan cells. Fetching of parallel data from parallel input terminals and transfer to the boundary scan cells are performed at a time.

Testing method for electronic apparatus

An integrated circuit for boundary scan is achieved to be simple structure. A testing apparatus 6 provides a testing data to a serial input port SI of a integrated circuit IC1 via a external terminal unit 2. The testing data is output to a parallel input port PI of the integrated circuit IC2 from a parallel output port SO of the integrated circuit IC1, then the testing data is output from the serial output port SO. The testing apparatus 6 compares with the testing data outputted to the integrated circuit IC1 and the testing data outputted from the integrated circuit IC2 so that a state of connection is detected between the parallel output port PO of the integrated circuit IC1 and the parallel input port PI of the integrated circuit IC2. The construction of the integrated circuits can be simplified by using both of inputting and outputting of the serial interface SIF.

Apparatus and method for testing the interconnection between integrated

A signal from an input terminal (1) is supplied to a video signal processing circuit (2) which derives a carrier chrominance signal. The carrier chrominance signal is supplied through a low-pass filter (3) to an A/D converter circuit (4). A signal converted by the A/D converter circuit (4) is supplied to a bandpass filter (5) which limits the band of the chrominance signal. A signal from the bandpass filter (5) is supplied to a decoder circuit (6) which alternately derives color difference signals (R-Y) and (B-Y). The signal from the decoder circuit (6) is supplied to a decimation filter (7) which effects a decimation. The signal thus decimated is supplied to a multiplexer (8) and thereby generated as 2-bit series data. A signal from the multiplexer (8) is supplied to a CNR (chroma noise reducer) circuit (9). Thus, the number of bits can be reduced without reducing the number of lines of a chroma signal and data gradation.

Chrominance signal processing circuit for a chroma-signal noise reducer

An adaptively controlled noise reduction device in which an input video signal is supplied to first, second, and third adders and in which an output of the first adder is supplied to the second adder via a memory responsive to a controller whereby the memory provides a controllable delay. An output of the second adder is supplied via a first coefficient multiplication unit having variable attenuation that is controlled by the controller to the first adder as well as via a second coefficient multiplication unit having variable attenuation that is controlled by the controller to the third adder. A change-over switch responsive to the controller outputs either a signal from the third adder or from the memory. Therefore, a signal is output even during the delay period produced by the memory when the signal is delayed between the first and second adders.

Adaptively controlled noise reduction device for producing a continuous

A digital image signal processing circuit for use in a VTR with camera has a signal input terminal to which an image pickup output signal or a video signal is supplied, an analog to digital converter for producing a digital image pickup output signal based on the image pickup output signal or a digital video signal based on the video signal, a digital signal processing portion including first, second and third digital signal processing circuit blocks, a system controller for conducting the change of operation, the change of circuit configuration or the change of circuit coefficient in each of the first, second and third digital signal processing circuit blocks, and signal output terminals from which recording luminance and carrier chrominance signals produced by the digital signal processing portion are derived. Each of the first, second and third digital signal processing circuit blocks performs efficiently various kinds of digital processing to the digital image pickup output signal or the digital video signal.

Digital image signal processing circuits

A video signal processing apparatus for a video camera having a video tape recording and reproducing device integrated therewith. The apparatus includes an automatic phase control (APC) circuit for controlling the phase of a color signal component contained in a video signal, a generating circuit having a microcomputer for generating a control signal for controlling the iris, focus and white balance of a video signal supplied from the video camera, and a digital operation circuit which is commonly used by the APC and generating circuits. The digital operation circuit includes an input device for receiving an output signal from the APC circuit and the video signal from the video camera, a processing device for processing the output signal and the video signal received by the input device, a device for supplying respective processed signals from the processing device to the APC and generating circuits, and a control device for controlling the input device, the processing device and the supplying device.

Video signal processing apparatus for controlling exposure, focus, and

A logical comb filter comprising a logic decision section for making logical decisions on the selection of signals and a signal generating section for generating signals to be selected according to the logical decisions made by the logic decision section. In the signal generating section, a band pass filter extracts from the input of a composite video signal a signal component centering on a color subcarrier frequency, and a first and a second delay line generate three line signals based on an inverted output downstream of the band pass filter. The inverted output is a main signal. The line signals are apart from one another by one horizontal scanning period. The signal generating section further comprises a first mean level calculator for calculating the mean level between the main signal and a first delay signal obtained as the inverted output downstream of the first delay line, and a second mean level calculator for calculating the mean level between the first delay signal and a second delay signal obtained as the inverted output downstream of the second delay line. One of the output signals and the first delay signal is selected by a changeover switch. In the logical decision section, comparisons are made between the three line signals in terms of level and, if the level of the first delay signal falls between the other two signal levels, the changeover switch selects the first delay signal; otherwise the output signal of the first or second mean level calculator is selected in accordance with the level relationship between the three line signals.

Logical comb filter

Semiconductor apparatus

Signal processing apparatus for processing a color video signal formed of a luminance signal and a color carrier signal reproduced from a magnetic tape, in which the signals include respective crosstalk components produced from the tracks adjacent the track being traced. The color video signal was originally recorded so that the crosstalk components are frequency interleaved relative to the signal in the track being reproduced, and signal processing apparatus permits the luminance and color carrier signals to be processed and the respective crosstalk components eliminated using only a single time delay element for both luminance and color carrier crosstalk components. The single delay unit is part of a comb filter and is particularly adapted for fabrication as a CCD element.

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Tokyo, Japan

Toshitaka Senuma