Sanyo Electric Co., Ltd.

Toshitaka Kuma

Hiroshi Watanabe

Koichi Tada

A digital signal processor () arithmetically determines a comparison level for comparing each signal component by determining a comparison level of comparators (and) for comparing a fine clock mark signal such that a larger weight is assigned to the comparison level of the signal component already compared. The comparators (and) compare the fine clock mark signal with reference to a level set on a peak side and a level set on a bottom side. When digital signal processor () receives the comparison signal from one of the comparators (and) prior to the comparison signal sent from the other, the digital signal processor produces a fine clock mark detection signal FCMT based on the comparison signal sent from a comparator (). Thereby, the clock can be accurately produced based on the fine clock mark signal even when a signal component having a larger amplitude than that of the fine clock mark signal is detected.

Optical disk apparatus capable of generating clock accurately

The optical disk apparatus is provided with a Viterbi decoder and an expected value correction circuit. The branch metric operation unit calculates first, second and third errors between sampling data and expected values, and outputs them to the expected value correction circuit. The expected value correction circuit extracts the sampling data in a region where its variation is small based on the first, second and third errors, calculates the average values of the extracted sampling data to correct the first, second and third expected values, and outputs the corrected expected values to the branch metric operation unit. The Viterbi decoder performs Viterbi decoding of the sampling data based on the first, second and third corrected expected values. Thus, high-precision Viterbi decoding is permitted even if the amplitude value of the reproduction signal varies.

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Gifu, Japan

Toshitaka Kuma