Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Matsushita Electronics Corporation

Matsushita Electrons Corporation

Toshitaka Hibi

Susumu Akamatsu

Yoshiaki Kato

Toshiyuki Kitagawa

Toyoyuki Shimazaki

Takehiko Ueda

Tatsuya Obata

Toshiharu Hirata

Tadami Shimizu

Hisashi Ogawa

Motohiro Sakata

Toshiaki Shimizu

Takatoshi Yasui

Shunsuke Kugo

Kouji Tsuyuki

Kazuo Hayama

Sayori Hirose

Keiko Hashimoto

Hideo Yokoe

A capacitor includes a capacitor element, a bottomed, cylindrical, metallic case, a metallic terminal plate, and a sealing rubber. A flange is provided along the outer circumference of the terminal plate. The flange is brought into contact with the bottom face of the sealing rubber for positioning. The case is wrung from the outside thereof so as to compress the sealing rubber. The sealing rubber has at least one of a ring-shaped top projection wall projecting between the metallic case and the terminal plate on the top face thereof, and a ring-shaped bottom projection wall projecting between the metallic case and the flange on the bottom face thereof.

Cylindrical capacitor employing electrolyte solution

An electric double-layer capacitor includes a cylindrical case having a bottom, a side surface, and an opening, a capacitor element accommodated in the case, the capacitor element, a driving electrolyte accommodated in the case, and a terminal plate provided at the opening of the case. The capacitor element includes a first electrode and a second electrode extending in a direction opposite to the first electrode. The second electrode is joined to the bottom of the case. The first and second electrodes are tilted away from the center axis of the capacitor element. In this electric double-layer capacitor, electrodes of the capacitor element are connected to the case and sealing plate reliably.

Electric double layer capacitor and method for manufacturing same

A capacitor includes a wound element, and externally take-out electrode members corresponding respectively to a first pole and a second pole and connected to each one of end faces of the wound element. This capacitor features that the wound element is positively fixed to the externally take-out electrode members, and has advantageously a small internal resistance. Collectors in inner circumference region of the wound element are bent in an opposite direction to a core of a winding shaft, and collectors in an outer circumference region are bent toward the core of the winding shaft. End faces of these collectors are connected to a lid, thereby forming a first pole of the capacitor, and end faces of those collectors are connected to a housing, thereby forming a second pole of the capacitor.

Capacitor having collectors with separate regions between innermost and outermost circumferences of a wound element

After a gate insulating film, a gate electrode and an on-gate protective layer have been formed in this order on an Si substrate, lightly-doped source/drain regions are formed in the substrate. First and second sidewalls are formed on the sides of the gate electrode and then heavily-doped source/drain regions are formed by implanting dopant ions using these sidewalls as a mask. After the second sidewall has been selectively removed, pocket implanted regions are formed and an overall protective film is deposited. Thereafter, an interlevel dielectric film is deposited, contact holes are formed to reach the heavily-doped source/drain regions and then plug electrodes are formed. Since the second sidewall has already been removed when the overall protective film is deposited, the gap between adjacent gate electrodes is not completely filled in. Accordingly, it is possible to provide a method for fabricating a semiconductor device contributing to device miniaturization without causing a shortcircuit between the gate electrode and a contact member.

Semiconductor device

A semiconductor storage unit and a method of manufacturing the same are provided. In the semiconductor storage unit, the formation of a gate electrode within a semiconductor substrate decreases the occurrence of a short circuit between conductive layers, provides an excellent electric connection in a connection hole between the semiconductor substrate and a conductive layers, and also reduces the number of manufacturing processes. In a semiconductor substrate, unit memory cells and are formed by providing a gate electrode in a region where a second opening is formed in a first opening, a first impurity-diffusion layer, a second impurity-diffusion layer, a third impurity-diffusion layer, a bit line, a charge-storage electrode, a capacity insulating film, and a plate electrode. Regions where the second opening is not formed are isolation regions and between memory cells. Consequently, a short circuit between the gate electrode and the other conductive layers does not occur easily and connection holes and can be made shallower, thus obtaining an excellent electric connection inside the connection holes.

Semiconductor storage unit and method of manufacturing the same

A method for fabricating a semiconductor device includes the steps of: forming a doped layer of a first conductivity type within a surface region of a semiconductor substrate; forming a recess by depositing an insulating film on the semiconductor substrate and then removing at least the insulating film in a region thereof where a gate electrode is to be formed; forming a gate insulating film on the surface of the semiconductor substrate, which is exposed inside the recess; and forming the gate electrode by filling in the recess with a conductive film.

Method for fabricating semiconductor device

Formed in a second interlayer dielectric are a first contact hole and a second contact hole. The first and second contact holes each extend to a first-level interconnect line. Tungsten is formed on the entirety of a substrate to form a first plug, a second plug, and a tungsten layer. A silicon oxide layer is formed. Thereafter, a patterning process is carried out to form a second-level interconnect line which is connected with the first plug and a top protective layer, and the top of the second plug remains exposed. A sidewall is formed on the side surfaces of the second-level interconnect line and the top protective layer. Subsequently, a third-level interconnect line, which is connected with the exposed second plug, is formed. Such arrangement not only reduces the number of contact hole formation masks, it also cuts down the number of fabrication steps. Further, the aspect ratio of the second contact hole becomes lower thereby achieving highly reliable semiconductor devices.

Semiconductor device and associated fabrication method

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Kyoto, Japan

Toshitaka Hibi