Kabushiki Kaisha Toshiba

Kioxia Corporation

Toshiba Memory Corporation

Toshitada Saito

Kunihiko Yamagishi

Akihisa Fujimoto

Jun Hasegawa

Toshio Fujisawa

Atsushi Kondo

Noriya Sakamoto

Masahiro Okada

Koichi Tanaka

Shuichi Obayashi

Ichiro Seto

Takashi Ueno

Taku Nishiyama

Takafumi Ohishi

Yoshimitsu Shimojo

Katsuyoshi Watanabe

Hideki Kawamura

According to one embodiment, there is provided a memory card including a first surface, a second surface, and 1to Nterminal groups. The first surface includes first to Nrows, where N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1to Nterminal groups are placed in the first to Nrows. The 1terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kterminal group, where K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.

Memory card with multiple modes, and host device corresponding to the memory card

According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

Interface system

A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.

Semiconductor device and memory system

A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8 b/10 b coding for the symbol. The transmission unit transmits the symbol coded by the 8 b/10 b coding unit to the host apparatus.

A memory card includes a first surface, a second surface, and 1to Nterminal groups. The first surface includes first to Nrows, wherein N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1to Nterminal groups are placed in the first to Nrows. The 1terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kterminal group, wherein K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.

According to one embodiment, a semiconductor storage device includes a housing, a plurality of terminals, signal terminals, a controller, signal wiring, and a memory. The housing has a first face and a second face opposite to the first face. The plurality of terminals is exposed to the first face, extends in a first direction, and is spaced apart in a second direction intersecting with the first direction. A signal terminal included in the plurality of terminals has a first end in the first direction, and a second end opposite to the first end in the first direction, the second end being closer to a contact position with a socket contact than the first end. The controller is located in the housing. The signal wiring extends from the first end in the housing and electrically connects the first end and the controller. The memory is electrically connected to the controller in the housing.

Semiconductor storage device

According to one embodiment, a receiving system includes a first receiving circuit and a second receiving circuit each receiving a differential signal with a positive phase signal and a negative phase signal, and a controller controlling the first and second receiving circuits. The first receiving circuit comprises a first differential amplifier outputting a first signal in a first time frame in which a polarity of the differential signal does not change dependent on a passage of time. The second receiving circuit comprises a second differential amplifier outputting a second signal in a second time frame in which the polarity of the differential signal changes dependent on the passage of time.

Growing community of inventors

Yokohama, Japan

Toshitada Saito