Hitachi, Ltd.

Other

Renesas Technology Corp.

Nippon Gakki Seizo Kabushiki Kaisha

Hitachi Ulsi Systems Co., Ltd.

Renasas Technology Corporation

Toshiro Takahashi

Kazuo Koide

Tadao Tokushima

Noboru Tsuya

Kazuhisa Suzuki

Yusuke Nonaka

Yasunobu Yanagisawa

Akira Yamagiwa

Masaaki Ohkawa

Hirokatsu Hayashi

Hideki Osaka

Takehisa Hayashi

Toshitsugu Takekuma

Yukio Wakui

Kenichi Ishibashi

Shunsuke Toyoshima

Shinichi Suzuki

Takashi Muto

Yasuhiro Fujimura

Tsutomu Goto

Kaoru Moriwaki

Masahiko Nagai

Takeshi Isezaki

Yoshifumi Suzuki

Toyohito Ikeya

Tatsuhiro Aida

Masaharu Kimura

Fumihiko Shirotori

The invention provides a technique that enables a correct discrimination of reception data, when the supply voltage of a semiconductor integrated circuit having a simultaneous bi-directional interface is decreased. The data transmission system is provided with input circuits constituting a simultaneous bi-directional interface by the number of reference voltages used. Each of the input circuits is supplied with a fixed reference voltage, the input circuit supplied with a higher reference voltage employs a differential amplifier with n-channel MOSFETs served as input differential devices, and the input circuit supplied with a lower reference voltage employs a differential amplifier with p-channel MOSFETs served as input differential devices, in which selectors switch the outputs of the two differential amplifiers in correspondence with the output data of their own. Thus, the system attains the reception data.

Data transmission system

Disclosed herewith is a semiconductor integrated circuit provided with a differential input circuit that can transmit data signals fast to an internal circuit free from distortion of their waveforms without increasing the subject chip in size. The differential input circuit is provided with a pair of first differential input transistors used to amplify mainly the low frequency components of those input signals and having gate terminals connected to a pair of input terminals that receive inputs of differential signals respectively, as well as a pair of second differential input transistors used mainly to amplify high frequency components of those input signals and having control terminals connected to a pair of input terminals that receive inputs of differential signals respectively through capacitance elements. The pairs of first and second differential transistors are connected to each other through a differential connection point (common source).

Semiconductor integrated circuit device and semiconductor integrated circuit

A method is provided for manufacturing an integrated circuit device having a plurality of wiring layers including a first wiring layer which is not the upper most layer among the plurality of wiring layers and a second wiring layer higher than the first wiring layer in the plurality of wiring layers. An interlayer dielectric film is provided to cover the first wiring layer. Holes are then formed in the interlayer dielectric film and a mask film is formed to cover some of the holes. Etching using the mask film is then carried out and an insulating film formed on the interlayer dielectric film is removed, including the bottoms and/or insides of the holes. The mask film is then removed and a conductive member is formed inside the holes.

Method of manufacturing a semiconductor integrated circuit device having a plurality of wiring layers and mask-pattern generation method

A level conversion circuit is composed of a level shift circuit for supplying a level-converted signal in the same phase as the input signal and a signal in the reverse phase thereto and a follow-up circuit responsive to the earlier of the output signals of the level shift circuit for generating an output signal, wherein the follow-up circuit consists of an inverter circuit in which two p-channel type MOS transistors and two n-channel type MOS transistors are connected in series between a first voltage terminal and a second voltage terminal, of which one pair is used as input transistors and the remaining pair of transistors are subjected to feedback based on the output signal of the level shift circuit to be quickly responsive to the next variation.

Level shift circuit and semiconductor integrated circuit

Noise of a low frequency band, generated inside a logic circuit, is remarkably reduced. A semiconductor integrated circuit device is provided with: a high voltage supply circuit generating, from a high voltage external power supply that is externally input, a high voltage internal power supply having a certain voltage level; and a low voltage supply circuit generating, from a low voltage external power supply that is externally input, a low voltage internal power supply having a certain voltage level. In inputting/outputting a signal between a logic circuit block and an I/O unit, a signal level is shifted through a level shifter unit. Since the logic circuit block is operated by the high voltage internal power supply and the low voltage internal power supply, the inductance in the semiconductor integrated circuit device is not subjected directly to DC fluctuation in consumed currents. Therefore, the characteristic impedance of power supply becomes equivalently smaller, thereby reducing low frequency noise.

Semiconductor integrated circuit device and electronic system

A capacitive element Chaving a small leakage current is formed by utilizing a gate oxide filmB thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element Chas a gate electrodeE. A part of the gate electrodeE is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power supply voltage.

Semiconductor integrated circuit device and method of manufacturing the same

A capacitive element C having a small leakage current is formed by utilizing a gate oxide film B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C has a gate electrode E. A part of the gate electrode E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power supply voltage.

A capacitive element C having a small leakage current is formed by utilizing a gate oxide film B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C has a gate electrode E. A part of the gate electrode E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power-supply voltage.

A bus system with an improved propagation velocity, comprising main lines, and a plurality of stub lines provided on a one-to-one correspondence with a plurality of modules, and connecting the corresponding modules to the main lines.

Bus system and circuit board

A capacitive element C having a small leakage current is formed by utilizing a gate oxide film 9B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C has a gate electrode E. A part of the gate electrode E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power-supply voltage.

Semiconductor integrated circuit device

A capacitive element C having a small leakage current is formed by utilizing a gate oxide film B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C has a gate electrode E. A part of the gate electrode E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the may reliably operate even at a low power-supply voltage.

Method of manufacturing semiconductor integrated circuit device

When signal transmission is performed between two semiconductor integrated circuit devices in synchronization with a clock signal using a small signal amplitude relative to an operating voltage of the two semiconductor integrated circuit devices, a received signal is held in the receiving semiconductor integrated circuit device in synchronization with the clock signal while the small signal amplitude of the held signal is kept substantially without change. The received signal having the small signal amplitude is amplified along a signal transmission path including a combined logic circuit to a subsequent latch circuit of the receiving semiconductor integrated circuit device.

Semiconductor integrated circuit device and low-amplitude signal receiving method

A semiconductor integrated circuit including an input circuit constituted as a single-input differential circuit which has a first MOSFET to whose gate a reception signal with a small amplitude with respect to a power supply voltage is supplied and a second MOSFET to whose gate a reference voltage corresponding to an intermediate value of the reception signal is supplied. A dummy circuit is provided and transmits substantially the same power supply noise as the power supply noise transmitted to the gate of the first MOSFET through a electrostatic protection circuit provided to an external terminal which receives the reception signal.

Growing community of inventors

Hamura, Japan

Toshiro Takahashi