Nissan Motor Company Limited

Toshiro Shinohara

Hiroyuki Kaneko

Tetsuya Hayashi

Masakazu Kobayashi

Yuki Nakajima

Masakatsu Hoshi

Yoshio Shimoida

Teruyoshi Mihara

Yutaro Kaneko

Yasuhiko Kitajima

Masahiro Tsukamoto

Tadayuki Hatsuda

Makoto Iwashima

Kouichirou Yonekura

Akihiro Hanamura

Hideaki Tanaka

Shigeharu Yamagami

Kenji Yao

Masanori Yamagiwa

Patrick J French

A drive unit for an electric vehicle is comprised of a motor, an inverter which supplies alternating current electric power to the motor, a speed reducer which is connected to the motor, and a cooling system which cools the motor, the inverter and the speed reducer. The speed reducer reduces a revolution speed of a mechanical output of the motor. The cooling system comprises a heat exchanger at which first refrigerant for receiving heat of at least one of the motor and the inverter receives heat of second refrigerant for receiving heat of at least one of the motor and the speed reducer.

Drive unit for electric vehicle

An aspect of the present invention provides a semiconductor device that includes, a first semiconductor body of a first conductivity type, a first switching mechanism provided on the first semiconductor body, configured and arranged to switch on/off current flowing through the semiconductor device, and a first reverse-blocking heterojunction diode provided on the semiconductor body, configured and arranged to block current reverse to the current switched on/off by the first switching mechanism.

Semiconductor device

A stacked semiconductor module encompasses (a) a upper switching element having a first semiconductor chip, a first top electrode disposed at a top surface of the first semiconductor chip, a first bottom electrode disposed at a bottom surface of the first semiconductor chip, and a first control electrode configured to control conduction between the first top and first bottom electrodes; (b) a first wiring plate disposed beneath the upper switching element, electrically connected to the first bottom electrode; and (c) a lower switching element disposed beneath the wiring plate, having a second semiconductor chip, a second top electrode disposed at a top surface of the second semiconductor chip, electrically connected to the first wiring plate, a second bottom electrode disposed at a bottom surface of the second semiconductor chip, and a second control electrode configured to control conduction between the second top and second bottom electrodes.

Stacked semiconductor module and assembling method of the same

An integrated drive motor unit which is integrally constituted of a motor, an inverter and a reducer differential unit arranged in a row, and a frame member. The reducer differential unit is connected to an output shaft of the motor, and distributes torque of the motor to a pair of axles, one of which passes through the inverter. The frame member constitutes a part of the motor and a part of the reducer differential unit, and has a portion surrounding the axle passing through the inverter. The inverter is disposed outside the frame member.

Integrated drive motor/differential/inverter unit with improved housing for a vehicle

An a.c. motor-inverter integrated drive unit comprises an a.c. motor powered by an alternating current. The motor includes a rotor rotatable about a rotation axis, a plurality of stator cores arranged about the rotation axis at evenly spaced intervals to constitute a cylindrical stator structure, a plurality of stator coils disposed on the stator cores respectively and a plurality of cooling passages formed in the stator cores respectively. An inverter is combined with the motor. The inverter converts a direct current to an alternating current and includes a plurality of power drivers which are arranged on the stator cores respectively. Wire members are used for connecting the power drivers and the stator coils respectively.

A.C. motor-inverter integrated drive unit

A UMOS semiconductor device has a surge absorbing structure around a drain lead region. A surge absorbing region such as an anode region or a region forming a punch-through or reach-through structure is formed near the drain lead region, and surrounded by a source region or source regions. The surge absorbing region forms a diode such as a zener diode with a highly doped buried layer or a drain region. With the diode, the surge absorbing structure controls the electric field around the drain lead region and thereby protects the gate insulating film from being damaged by a drain surge.

A semiconductor structure having a plurality of drivers in and on the same semiconductor substrate is arranged to increase the density of integrated components and reduce the on resistance. The semiconductor structure employs a double layer interconnection structure having source and drain electrodes at two different levels, and an insulated gate electrode in a groove formed the semiconductor substrate. Each drain lead region having a low resistivity material extends from the upper surface of the substrate to a low resistivity buried layer. Each drain opening is surrounded by a source zone formed with a series of source holes or a long and narrow source slot, and this basic pattern is regularly repeated in a plane.

Groove-type semiconductor device

A semiconductor accelerometer, including a weight and a cantilevered beam formed in a silicon semiconductor substrate as a frame having a (100) surface, and a strain sensing device formed in a surface portion near a support portion of the cantilevered beam, the silicon cantilevered beam having a triangular cross section defined by one (100) surface and two (111) surfaces or a pentagonal cross section defined by one (100) surface, two (110) surfaces and two (111) surfaces. A method for producing the semiconductor accelerometer is also disclosed.

Semiconductor accelerometer having a cantilevered beam with a triangular

A piezoresistive device, in which separation grooves having a cross section defined by four (111) planes and including side walls of a silicon oxide film are formed in a surface area of a semiconductor substrate having a surface of (100) plane, and at least one piezoresistor having an inversed triangular cross section defined by one (100) plane and two (111) planes is formed in the surface area of the semiconductor substrate and is surrounded by the separation grooves for separating the piezoresistor from the semiconductor substrate.

Piezoresistive semiconductor device suitable for use in a pressure sensor

A semiconductor device comprises a semiconductor base having an aperture to form a first cantilever having a weight integral therewith, a second cantilever and a third cantilever. The second and third cantilevers are formed on the opposite sides of the first cantilever. The semiconductor device also comprises first and second piezo resistors formed in the first cantilevers, a third piezo resistor formed in the second cantilever, and a fourth piezo resistor formed in the third cantilever. The first, second, third and fourth piezo resistors are connected in a four-arm bridge circuit having a first pair of opposite arms comprised of the first and second piezo resistors, respectively, and a second pair of opposite arms comprised of the third and fourth piezo resistors, respectively, to compensate the first and second piezo resistors for temperature.

Pressure sensitive semiconductor device with cantilevers

A thin film semiconductor device has an n-type collector region formed in a semiconductor thin film on an insulating substrate, a p-type base region formed in the collector region, and an n-type emitter region. The base and emitter regions are formed by successive diffusion steps of p-type impurities and n-type impurities by using the same mask through the same diffusion window in such a manner than the base width is determined by a difference between the lateral diffusion distance of the p-type impurities and the lateral diffusion distance of the n-type impurities from the common diffusion window.

Thin film semiconductor device

In order to improve latchup withstanding capability, a CMOS device is provided with at least one recombination layer which is buried in either or both substrate regions of a pMOS and a nMOS at such a position that a depletion layer formed at a pn junction between both substrate regions of the pMOS and nMOS does not reach the recombination layer. The recombination layer is a polycrystalline silicon or amorphous silicon layer having plentiful carrier recombination centers, or a layer having plentiful traps formed by ion implantation, or a layer of a compound semiconductor having a small band gap.

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Yokosuka, Japan

Toshiro Shinohara